AD7490BCP(RevA) 查看數據表（PDF） - Analog Devices
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AD7490BCP Datasheet PDF : 24 Pages
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AD7490
ADD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table II. Channel Selection
ADD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ADD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input
Channel
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
Table III. Power Mode Selection
PM1
1
1
0
0
PM0
1
0
1
0
Mode
Normal Operation
In this mode, the AD7490 remains in full
power mode regardless of the status of any of
the logic inputs. This mode allows the fastest
possible throughput rate from the AD7490.
Full Shutdown
In this mode, the AD7490 is in full shut-down
mode, with all circuitry on the AD7490 powering
down. The AD7490 retains the information
in the Control Register while in full shutdown.
The part remains in full shutdown until these
bits are changed in the Control Register.
Auto Shutdown
In this mode, the AD7490 automatically enters
shutdown mode at the end of each conversion
when the Control Register is updated. Wake-up
time from shutdown is 1 µs and the user should
ensure that 1 µs has elapsed before attempting
to perform a valid conversion on the part in
this mode.
Auto Standby
In this standby mode, portions of the AD7490
are powered down, but the on-chip bias gen-
erator remains powered-up. This mode is
similar to Auto Shutdown and allows the part
to power-up within one dummy cycle, i.e.,
1 µs with a 20 MHz SCLK.
For more information, see the Modes of Operation section.
SEQUENCER OPERATION
The configuration of the SEQ and Shadow Bits in the Control
Register allows the user to select a particular mode of operation
of the sequencer function. Table IV outlines the four modes of
operation of the Sequencer.
Table IV. Sequence Selection
SEQ SHADOW
0
0
0
1
1
0
1
1
Sequence Type
This configuration means the sequence
function is not used. The analog input
channel selected for each individual
conversion is determined by the contents
of the channel address bits ADD0
through ADD3 in each prior write
operation. This mode of operation reflects
the normal operation of a multichannel
ADC, without sequencer function being
used, where each write to the AD7490
selects the next channel for conversion.
(See Figure 2.)
This configuration selects the Shadow
Register for programming. After the write
to the Control Register, the following
write operation will load the contents
of the Shadow Register. This will program
the sequence of channels to be converted
on continuously with each successive
valid CS falling edge. (See Shadow Regis-
ter, Table V, and Figure 3.) The channels
selected need not be consecutive.
If the SEQ and SHADOW Bits are set
in this way, then the sequence function
will not be interrupted upon completion
of the WRITE operation. This allows
other bits in the Control Register to be
altered while in a sequence without
terminating the cycle.
This configuration is used in conjunction
with the channel address bits ADD3 to
ADD0 to program continuous conver-
sions on a consecutive sequence of
channels from Channel 0 through to a
selected final channel as determined by
the channel address bits in the Control
Register. (See Figure 4.)
–10–
REV. A
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