AD7490BCP(RevA) 查看數據表（PDF） - Analog Devices
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AD7490BCP Datasheet PDF : 24 Pages
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AD7490
TIMING SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
fSCLK2
tCONVERT
tQUIET
t2
t33
t3b4
t43
t5
t6
t7
t85
t9
t10
t11
t12
Limit at TMIN, TMAX
VDD = 3 V
VDD = 5 V
10
16
16 ϫ tSCLK
50
10
20
16 ϫ tSCLK
50
12
20
30
60
0.4 tSCLK
0.4 tSCLK
15
15/50
20
5
20
1
10
14
20
40
0.4 tSCLK
0.4 tSCLK
15
15/50
20
5
20
1
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
µs max
Description
Minimum Quiet Time Required between Bus
Relinquish and Start of Next Conversion
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Delay from CS to DOUT Valid
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/
Auto Shutdown/Auto Standby Modes
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
(See Figure 1.) The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be
taken when interfacing to account for data access time t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK
frequency with which the user’s system can operate. (See Serial Interface section.)
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE V.
4t3b represents a worst-case figure for having ADD3 available on the DOUT line, i.e., if the AD7490 went back into three-state at the end of a conversion and some
other device took control of the bus between conversions, the user would have to wait a maximum time of t3b before having ADD3 valid on DOUT line. If the DOUT
line is weakly driven to ADD3 between conversions, then the user would typically have to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing
ADD3 valid on DOUT.
5t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
–4–
REV. A
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