AD7928BRU-REEL7 查看數據表（PDF） - Analog Devices
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AD7928BRU-REEL7 Datasheet PDF : 24 Pages
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AD7908/AD7918/AD7928
AD7918–SPECIFICATIONS (AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless
otherwise noted.)
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)2
61
Signal-to-Noise Ratio (SNR)2
61
Total Harmonic Distortion (THD)2
–72
Peak Harmonic or Spurious Noise
(SFDR)2
–74
Intermodulation Distortion (IMD)2
Second Order Terms
–90
Third Order Terms
–90
Aperture Delay
10
Aperture Jitter
50
Channel-to-Channel Isolation2
–85
Full Power Bandwidth
8.2
1.6
dB min
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 ϫ REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
10
Bits
±0.5
LSB max
±0.5
LSB max Guaranteed No Missed Codes to 10 Bits
Straight Binary Output Coding
±2
LSB max
±0.2
LSB max
±0.5
LSB max
±0.2
LSB max
–REFIN to +REFIN Biased about REFIN with
±0.5
LSB max Twos Complement Output Coding
±0.2
LSB max
±2
LSB max
±0.2
LSB max
±0.5
LSB max
±0.2
LSB max
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to REFIN
0 to 2 ϫ REFIN
±1
20
V
V
µA max
pF typ
RANGE Bit Set to 1
RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
2.5
V
±1
µA max
36
k⍀ typ
0.7 ϫ VDRIVE
0.3 ϫ VDRIVE
±1
10
V min
V max
µA max
pF max
VDRIVE – 0.2
0.4
V min
V max
±1
µA max
10
pF max
Straight (Natural) Binary
Twos Complement
±1% Specified Performance
fSAMPLE = 1 MSPS
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
ISINK = 200 µA
Coding Bit Set to 1
Coding Bit Set to 0
CONVERSION RATE
Conversion Time
800
Track-and-Hold Acquisition Time
300
300
Throughput Rate
1
ns max
ns max
ns max
MSPS max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
See Serial Interface Section
–4–
REV. A
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