AD8158 查看數據表（PDF） - Analog Devices

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AD8158

6.5 Gbps Quad Buffer Mux/Demux

Analog Devices 

AD8158

The LOS_INT pin evaluates a logical OR of all LOS status

register bits for all enabled receivers. (LOS status registers are

located at 0x45, 0x85, and 0xC5.) The upper four bits in the

RXA, RXB, and RXC LOS status registers are sticky while the

four LSBs are continuously updated to indicate the instantaneous

status of LOS for an enabled receiver. The sticky bits are cleared

by writing 0 to the RXA, RXB, and RXC LOS status registers.

The LOS_INT pin remains high after an LOS event until all

sticky registers are cleared and all active status registers (for

example, Bits [3:0]) read 0.

The LOS_INT pin can be used to generate an interrupt for the

system control software. In a standard implementation, when

LOS_INT goes high, the system software registers the interrupt

and polls the RXA, RXB, and RXC LOS status registers to

determine which input lost signal and if the signal has been

restored.

LANE INVERSION: P/N SWAP

The receiver P/N swap function is a convenience intended to

allow the user to implement the equivalent of a board-level

routing crossover in a much smaller area while eliminating vias

(impedance discontinuities) that compromise the high frequency

integrity of the signal path.

A Note of Caution

Using this feature to correct an inversion downstream of the

receiver may require the user to be aware of the sign of the data

when switching connectivity (the mux/demux path). The

feature is available on a per-lane setting through Register 0x44,

Register 0x84, and Register 0xC4. Setting the bit true flips the

sign sense of the P and N inputs for the associated lane. The

default setting is 0 (no inversion).

TRANSMITTERS

The AD8158 transmitter offers programmable pre-emphasis,

programmable output levels, output disable, and transmit

squelch. The SEL4G pin lets the user lower the transmitter

frequency of maximum boost from 3.25 GHz to 2.0 GHz,

allowing the AD8158 to offer exceptional transmit channel

compensation for legacy applications (4.5 Gbps and slower).

OUTPUT LEVEL PROGRAMMING AND OUTPUT

STRUCTURE

The output level of the transmitter of each lane is independently

programmable. In pin control mode, a default output amplitude

of 800 mV p-p diff (±400 mV diff) is delivered (see Table 17).

Register-based control allows the user to set the transmitter

output levels on a per-port or per-lane basis to four predefined

levels. Port-level programming overwrites lane-level configuration.

The ALEV, BLEV, and CLEV bits in Register 0x49, Register 0x89,

and Register 0xC9, respectively, are used to set the output levels

for all transmitters. The A[3:0]OLEV[1:0], B[3:0]OLEV[1:0],

and C[3:0]OLEV[1:0] bits in Register 0x4C, Register 0x8C, and

Register 0xCC allow per-lane settings (see Table 23).

Table 17. Predefined Output Levels

[A/B/C]OLEV1

[A/B/C]OLEV0

0

0

0

1

1

0

1

1

Output Level

±200 mV diff

±300 mV diff

±400 mV diff (default)

± 600 mV diff

Note that the choice of output level influences the output

common-mode level. A 600 mV diff output level with a full PE

range requires a supply and output termination voltage of 2.5 V

or higher (VTTO, VCC ≥ 2.5 V).

PRE-EMPHASIS

Transmitter pre-emphasis levels can be set by pin control or

through the control registers. Pin control allows two settings of

PE, 0 dB, and 6 dB. The control registers provide seven levels of

PE. Note that a larger range of boost settings is available for

lower output levels.

Pre-emphasis can be programmed per-port or per-lane.

Register 0x49, Register 0x89, and Register 0xC9 set all outputs

in a port at once. Registers 0x4A, 0x4B, 0x8A, 0x8B, 0xCA, and

0xCB allow setting PE on a per-lane basis.

Table 18. Lane Inversion Bits

Address

Bit 7

Bit 6

0x44

0x84

0xC4

Bit 5

Bit 4

Bit 3

PNA3

PNB3

PNC3

Bit 2

PNA2

PNB2

PNC2

Bit 1

PNA1

PNB1

PNC1

Bit 0

PNA0

PNB0

PNC0

Function

P/N Swap A

P/N Swap B

P/N Swap C

Rev. 0 | Page 21 of 36

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