AD8158 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

AD8158

6.5 Gbps Quad Buffer Mux/Demux

Analog Devices 

AD8158

SQUELCH AND DISABLE

Each transmitter is equipped with disable and squelch controls.

Disable is a full power-down state: the transmitter current is

reduced to zero and the output pins pull up to VTTO, but there

is a delay of approximately 1 μs associated with re-enabling

the transmitter. Squelch simply reduces the output current to

submicroamp levels, again allowing both output pins to pull up

to VTTO through the output termination resistors. The transmit-

ter recovers from squelch in less than 100 ns.

SPEED SELECT

The SEL4G pin lets the user lower the transmitter frequency of

maximum boost from 3.25 GHz to 2.0 GHz, allowing the

AD8158 to offer exceptional transmit channel compensation for

legacy applications (4.5 Gbps and slower). SEL4G = 1 lowers the

frequency of maximum boost without sacrificing the amount of

boost delivered.

AD8158 POWER CONSUMPTION

There are several sections of the AD8158 that draw varying

power depending on the supply voltages, the type of I/O

coupling used, and the status of the AD8158 operation. Figure 41

shows a block diagram of these sections. Figure 42 summarizes

the power consumption of each section and is a useful guide as

the following sections are reviewed.

A power budget calculator is available on the AD8158 product

page at www.analog.com.

VTTI

VCC

DVCC

VTTO

VTT

IP_xx

IN_xx

AC-COUPLING CAPS

(OPTIONAL)

INPUT

TERMINATION

(VIN_DIFF_RMS)2

P=

100Ω

EQUALIZER

LOSS OF

SIGNAL

RECEIVER

SWITCH

OUTPUT

TERMINATIONS

P

=

IOUT

2

×

50Ω

50Ω

50Ω

50Ω

50Ω

IOUT

OPTIONAL COUPLING

CAPACITORS

P = (VOL) (IOUT)

VOL = VTTO – (IOUT × 25Ω)

VEE

Figure 41. AD8158 Power Distribution Block Diagram

Rev. 0 | Page 26 of 36

Share Link: