AD8158 查看數據表（PDF） - Analog Devices
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AD8158 Datasheet PDF : 36 Pages
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AD8158
Mnemonic
TXB Lane2/
TXB Lane 3
PE Setting
TXB Per-Lane
Level Setting
RXC Disable
RXC Setting
RXC LOS
Threshold
RXC LOS Ctrl
RXC Lane 1/
RXC Lane 0
Setting
RXC Lane 3/
RXC Lane 2
Setting
RXC P/N
Swap
RXC LOS
Status
TXC Disable
TXC Level/PE
Control
TXC Lane1/
TXC Lane 0
PE Setting
TXC Lane2/
TXC Lane 3
PE Setting
TXC Per-Lane
Level Setting
Addr. Bit 7
0x8B1
0x8C1 B3OLEV[1]
0xC0
0xC1
0xD0
Set to 0
0xD1 Set to 0
0xC21 C1EQ[3]
0xC31 C3EQ[3]
0xC41
0xC51
0xC8
0xC9
LOSC3
Sticky
0xCA1
0xCB1
0xCC1 C3OLEV[1]
Bit 6
B3PE[2]
B3OLEV[0]
Set to 0
Set to 0
C1EQ[2]
C3EQ[2]
LOSC2
Sticky
C1PE[2]
C3PE[2]
C3OLEV[0]
1 Per-lane registers.
Bit 5
B3PE[1]
B2OLEV[1]
THRBIT[5]
Set to 0
C1EQ[1]
C3EQ[1]
LOSC1
Sticky
CLEV[1]
C1PE[1]
C3PE[1]
C2OLEV[1]
Bit 4
B3PE[0]
B2OLEV[0]
THRBIT[4]
Set to 0
C1EQ[0]
C3EQ[0]
LOSC0
Sticky
CLEV[0]
C1PE[0]
C3PE[0]
C2OLEV[0]
Bit 3
Bit 2
B2PE[2]
Bit 1
B2PE[1]
Bit 0
B2PE[0]
B1OLEV[1]
RXDIS C3
CEQ[3]
THRBIT[3]
Set to 0
C0EQ[3]
B1OLEV[0] B0OLEV[1] B0OLEV[0]
RXDIS C2
CEQ[2]
THRBIT[2]
RXDIS C1
CEQ[1]
THRBIT[1]
RXDIS C0
CEQ[0]
THRBIT[0]
LOS_FILT
C0EQ[2]
LOS_GSEL LOS_ENB
C0EQ[1]
C0EQ[0]
C2EQ[3]
C2EQ[2]
C2EQ[1]
C2EQ[0]
PNC3
PNC2
LOSC3 Active
TXDIS C3
LOSC2
Active
TXDIS C2
CPE[2]
C0PE[2]
PNC1
LOSC1
Active
TXDIS C1
CPE[1]
C0PE[1]
PNC0
LOSC0
Active
TXDIS C0
CPE[0]
C0PE[0]
C2PE[2]
C2PE[1]
C2PE[0]
C1OLEV[1]
C1OLEV[0] C0OLEV[1] C0OLEV[0]
Default
0x00
0xAA
0x00
0x00
0x1C
0x07
0x00
0x00
0x00
0x00
0x20
0x00
0x00
0xAA
Rev. 0 | Page 33 of 36
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