AD9480(Rev0) 查看數據表（PDF） - Analog Devices
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AD9480 Datasheet PDF : 28 Pages
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AD9480
AD9480 EVALUATION BOARD
The AD9480 evaluation board offers an easy way to test the
device. It requires a clock source, an analog input signal, and a
3.3 V power supply. The clock source is buffered on the board to
provide the clocks for the ADC and a data-ready signal. The
digital outputs and output clocks are available at a 40-pin
connector, P10. The board has several different modes of
operation and is shipped in the following configuration:
• Offset binary
• Internal voltage reference
POWER CONNECTOR
Power is supplied to the board via 2 detachable 4-pin power
strips.
Table 11. Power Connector
Terminal
Comments
AVDD1 3.3 V
Analog supply for ADC ~ 150 mA
DRVDD1 3.3 V
Output supply for ADC ~ 40 mA
VCTRL1 3.3 V
Supply for support clock circuitry ~ 50 mA
Op amp, ext. ref Optional supply for op amp and ADR510
reference
1 AVDD, DRVDD, and VCTRL are the minimum required power connections.
2 LVEL16 clock buffer can be powered from AVDD or VCTRL LVEL16 buffer
jumper.
ANALOG INPUTS
The evaluation board accepts a 700 mV p-p analog input signal
centered at ground at SMB Connector J3. This signal is
terminated to ground through 50 Ω by R22. The input can be
alternatively terminated at the T1 transformer secondary by
R21 and R28. T1 is a wideband RF transformer providing the
single-ended-to-differential conversion, allowing the ADC to be
driven differentially, minimizing even-order harmonics. An
optional transformer, T4, can be placed if desired (remove T1,
as shown in Figure 41 and Figure 42).
The analog signal can be low-pass filtered by R31, C8, and
R29, C9 at the ADC input.
GAIN
Full scale is set by the sense jumper. This jumper applies a bias
to the sense pin to vary the full-scale range; the default position
is sense = ground, setting the full scale to 1 V p-p.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8351 op amp which can serve as a convenient solution for
dc-coupled applications. To use the AD8351 op amp, remove
R29, R31, and C3. Populate R40, R43, and R47 with 25 Ω
resistors, and populate C24, C28, C29, C30, C31, and C32 with
0.1 uF capacitors. Populate R38, R39, and R51 with a 10 Ω
resistor, and R44 and R45 with a 1 kΩ resistor. Populate R41
with a 1.2 kΩ resistor and R42 with a 100 Ω resistor. Populate
R52 with a 10 kΩ resistor.
CLOCK
The clock input is terminated to ground through 50 Ω at
SMA Connector J1. The input is ac-coupled to a high speed
differential receiver (LVEL16) that provides the required low
jitter, fast edge rates needed for best performance. J1 input
should be > 0.5 V p-p. Power to the LVEL16 is set to VCTRL
(default) or AVDD by jumper placement at the device.
OPTIONAL CLOCK BUFFER
The PCB has been designed to accommodate the SNLVDS1
line driver. The SNLVDS1 is used as a high speed LVDS-level
optional encode clock. To use this clock, please remove C2, C5,
and C6. Place a 0.1 uF capacitor on C34, C35, and C26. Place a
10 Ω resistor on R48 and place a 100 Ω resistor on R6. Place
R49 and R53 with a 0 Ω resistor. For best results using the LVDS
line driver, J1 input should be >2.5 V p-p.
OPTIONAL XTAL
The PCB has been designed to accommodate an optional
crystal oscillator which can serve as a convenient clock source.
The footprint can accept both through-hole and surface-mount
devices, including Vectron XO-400 and Vectron VCC6 family
oscillators.
VCC
OUT+
OUT–
VCC
GND
Figure 40. XTAL Footprint
To use either crystal, populate C26 and C27 with 0.1 uF capaci-
tors. Populate R49 and R53 with 0 Ω resistors. Place R54, R55,
R56, and R57 with 1 kΩ resistors. Remove C6 and C5. If the
Vectron VCC6 family crystal is being used, populate R48 with a
10 Ω resistor. If using the XO-400 crystal, place jumper E21 or
E22 to E23.
Rev. 0 | Page 19 of 28
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