AD9511BCPZ 查看數據表（PDF） - Analog Devices

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AD9511BCPZ

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

AD9511

SPECIFICATIONS

Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted.

Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.

PLL CHARACTERISTICS

Table 1.

Parameter

REFERENCE INPUTS (REFIN)

Input Frequency

Input Sensitivity

Self-Bias Voltage, REFIN

Self-Bias Voltage, REFINB

Input Resistance, REFIN

Input Resistance, REFINB

Input Capacitance

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

PFD Input Frequency

PFD Input Frequency

Antibacklash Pulse Width

Antibacklash Pulse Width

Antibacklash Pulse Width

CHARGE PUMP (CP)

ICP Sink/Source

High Value

Low Value

Absolute Accuracy

CPRSET Range

ICP Three-State Leakage

Sink-and-Source Current Matching

ICP vs. VCP

ICP vs. Temperature

RF CHARACTERISTICS (CLK2)2

Input Frequency

Min Typ

0

150

1.45 1.60

1.40 1.50

4.0 4.9

4.5 5.4

2

1.3

2.9

6.0

4.8

0.60

2.5

2.7/10

1

2

1.5

2

Input Sensitivity

Input Common-Mode Voltage, VCM

Input Common-Mode Range, VCMR

Input Sensitivity, Single-Ended

Input Resistance

Input Capacitance

CLK2 VS. REFIN DELAY

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 2 DM (2/3)

P = 4 DM (4/5)

P = 8 DM (8/9)

P = 16 DM (16/17)

P = 32 DM (32/33)

CLK2 Input Frequency for PLL

150

1.5 1.6

1.3

150

4.0 4.8

2

500

Max Unit Test Conditions/Comments

250 MHz

mV p-p

1.75 V

Self-bias voltage of REFIN1.

1.60 V

Self-bias voltage of REFINB1.

5.8 kΩ

Self-biased1.

6.3 kΩ

Self-biased1.

pF

100 MHz

100 MHz

45 MHz

ns

ns

ns

Antibacklash pulse width 0Dh<1:0> = 00b.

Antibacklash pulse width 0Dh<1:0> = 01b.

Antibacklash pulse width 0Dh<1:0> = 10b.

0Dh<1:0> = 00b. (This is the default setting.)

0Dh<1:0> = 01b.

0Dh<1:0> = 10b.

Programmable.

mA

With CPRSET = 5.1 kΩ.

mA

%

VCP = VCPS/2.

kΩ

nA

%

0.5 < VCP < VCPS − 0.5 V.

%

0.5 < VCP < VCPS − 0.5 V.

%

VCP = VCPS/2 V.

1.6 GHz

Frequencies > 1200 MHz (LVPECL) or

800 MHz (LVDS) require a minimum

divide-by-2 (see the Distribution Section).

mV p-p

1.7 V

Self-biased; enables ac coupling.

1.8 V

With 200 mV p-p signal applied.

mV p-p CLK2 ac-coupled; CLK2B capacitively

bypassed to RF ground.

5.6 kΩ

Self-biased.

pF

ps

Difference at PFD.

See the VCO/VCXO Feedback Divider—N (P, A, B)

section.

600 MHz

1000 MHz

1600 MHz

1600 MHz

1600 MHz

300 MHz

A, B counter input frequency.

Rev. A | Page 4 of 60

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