AD9511BCPZ 查看數據表（PDF） - Analog Devices

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AD9511BCPZ

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

AD9511

CLOCK OUTPUTS

Table 3.

Parameter

LVPECL CLOCK OUTPUTS

OUT0, OUT1, OUT2; Differential

Output Frequency

Output High Voltage (VOH)

Output Low Voltage (VOL)

Output Differential Voltage (VOD)

LVDS CLOCK OUTPUTS

OUT3, OUT4; Differential

Output Frequency

Differential Output Voltage (VOD)

Delta VOD

Output Offset Voltage (VOS)

Delta VOS

Short-Circuit Current (ISA, ISB)

CMOS CLOCK OUTPUTS

OUT3, OUT4

Output Frequency

Output Voltage High (VOH)

Output Voltage Low (VOL)

Min

VS − 1.22

VS − 2.10

660

250

1.125

Typ

VS − 0.98

VS − 1.80

810

360

1.23

14

Max

1200

VS − 0.93

VS − 1.67

965

800

450

25

1.375

25

24

Unit Test Conditions/Comments

Termination = 50 Ω to VS − 2 V

Output level 3Dh (3Eh) (3Fh)<3:2> = 10b

MHz See Figure 21

V

V

mV

Termination = 100 Ω differential; default

Output level 40h (41h)<2:1> = 01b

3.5 mA termination current

MHz See Figure 22

mV

mV

V

mV

mA Output shorted to GND

VS-0.1

Single-ended measurements;

B outputs: inverted, termination open

250

MHz With 5 pF load each output; see Figure 23

V

@ 1 mA load

0.1

V

@ 1 mA load

Rev. A | Page 6 of 60

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