ADG738 查看數據表（PDF） - Analog Devices

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ADG738

CMOS, Low Voltage, 3-Wire Serially-Controlled, Matrix Switches

Analog Devices 

ADG738/ADG739

Data Sheet

SCLK 1

16 DOUT

SYNC 2

15 GND

DIN 3

S1A 4

S2A 5

ADG739

TOP VIEW

(Not to Scale)

14 VDD

13 S1B

12 S2B

S3A 6

11 S3B

S4A 7

10 S4B

DA 8

9 DB

Figure 5. ADG739 Pin Configuration

Table 6. ADG739 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. These devices can accommodate serial input rates of up to 30 MHz.

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC

goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is

transferred on the falling edges of the following clocks. Taking SYNC high updates the switch

conditions.

3

DIN

Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial

clock input.

4, 5, 6, 7

S1A, S2A, S3A, S4A Source. May be an input or output.

8, 9

DA, DB

Drain. May be an input or output.

10, 11, 12, 13 S4B, S3B, S2B, S1B

Source. May be an input or output.

14

VDD

15

GND

Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.

Ground Reference.

16

DOUT

Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input

shift register on the rising edge of SCLK. This is an open drain output, which should be pulled to

the supply with an external resistor.

Rev. A | Page 8 of 20

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