ADIS16201 查看數據表（PDF） - Analog Devices

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ADIS16201

Programmable Dual-Axis Inclinometer/Accelerometer

Analog Devices 

Data Sheet

TIMING SPECIFICATIONS

TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.

Table 2.

Parameter

fSCLK

tDATARATE

tDATARATE

tSTALL

tSTALL

tcs

tDAV

tDSU

tDHD

tDF

tDR

tSFS

Description

Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)

Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)

Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)

Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)

Stall period, fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz)

Stall period, normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz)

Chip select to clock edge

Data output valid after SCLK edge

Data input setup time before SCLK rising edge

Data input hold time after SCLK rising edge

Data output fall time

Data output rise time

CS high after SCLK edge

1 Guaranteed by design, not tested.

Min1

0.01

0.01

32

42

10

12

48.8

24.4

48.8

5

TIMING DIAGRAMS

CS

SCLK

tDATA RATE

tSTALL

tSTALL = tDATA RATE – 16/fSCLK

Figure 2. SPI Chip Select Timing

ADIS16201

Typ

Max

Unit

2.5

MHz

1.0

MHz

μs

μs

μs

μs

ns

100

ns

ns

ns

5

12.5

ns min

5

12.5

ns min

ns typ

CS

SCLK

DOUT

DIN

tCS

1

MSB

W/R

2

3

4

5

6

tDAV

DB14

tDSU

DB13

DB12

tDHD

DB11

DB10

A5

A4

A3

A2

15

16

tSFS

DB2

DB1

LSB

D2

D1

LSB

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

Rev. C | Page 5 of 32

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