ADP3415 查看數據表（PDF） - ON Semiconductor
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ADP3415 Datasheet PDF : 10 Pages
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ADP3415–SPECIFICATIONS1 (TA = 0؇C to 100؇C, VCC = 5 V, VBST – VSW = 5 V, SD = 5 V, CDRVH = CDRVL = 3 nF,
unless otherwise noted.)
Parameter
Symbol
Conditions
Min Typ Max Unit
SUPPLY (VCC)
Quiescent Current2
Shutdown Mode
Operating Mode
ICCQ
VSD = 0.8 V
VSD = 5 V, No Switching
30
65 µA
1.2 2
mA
UNDERVOLTAGE LOCKOUT
(UVLO)
UVLO Threshold
UVLO Hysteresis
VCCUVLO
VCCHUVLO
3.9
4.15 4.5 V
0.05
V
LOW-SIDE DRIVER SHUTDOWN
(DRVLSD)
Input Voltage High3
Input Voltage Low3
Propagation Delay3, 4
(See Figure 3)
VIH
VIL
tpdlDRVLSD
tpdhDRVLSD
2.0
V
0.8 V
20
50 ns
10
30 ns
SHUTDOWN (SD)
Input Voltage High3
VIH
Input Voltage Low3
VIL
2.0
V
0.8 V
INPUT (IN)
Input Voltage High3
VIH
Input Voltage Low3
VIL
2.0
V
0.8 V
THERMAL SHUTDOWN (THSD)
THSD Threshold
THSD Hysteresis
TSD
THSD
TJ = TA
TJ = TA
165
°C
10
°C
HIGH-SIDE DRIVER (DRVH)
Output Resistance, DRVH–BST
Output Resistance, DRVH–SW
DRVH Transition Times4
(See Figure 4)
DRVH Propagation Delay4, 5
(See Figure 4)
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
VBST – VSW = 4.6 V
VBST – VSW = 4.6 V, VDLY = 0 V
RDLY ≥ 120 kΩ
1.5 3.5 Ω
0.85 2.0 Ω
20
30 ns
25
35 ns
10
22
40 ns
100
200 ns
40
70 ns
LOW-SIDE DRIVER (DRVL)
Output Resistance, DRVL–VCC
Output Resistance, DRVL–GND
DRVL Transition Times4
(See Figure 4)
DRVL Propagation Delay4, 5, 6
(See Figure 4)
SW Transition Timeout7
Zero-Crossing Threshold
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
tSWTO
VZC
VBST – VSW = 4.6 V
VBST – VSW = 4.6 V
VBST – VSW = 4.6 V
VBST – VSW = 4.6 V
VBST – VSW = 4.6 V
1.6 3.0 Ω
1.0 3.0 Ω
25
40 ns
20
30 ns
10
30
38 ns
10
25 ns
130
300 ns
1.6
V
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Including IBSTQ quiescent current.
3The signal source driving the pin must have 70 µA (typ) pull-down strength to make a high-to-low transient, and 20 µA (typ) pull-up strength to make a low-to-high
transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard
TTL logic level source.
4Guaranteed by characterization.
5For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.
6Propagation delay measured until DRVL begins its transition.
7The turn-on of DRVL is initiated after IN goes low by either VSW crossing a ~1.6 V threshold or by expiration of tSWTO.
Specifications subject to change without notice.
Rev. 6 | Page 2 of 10 | www.onsemi.com
–2–
REV. B
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