AIC1573 查看數據表（PDF） - Analog Intergrations

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AIC1573

5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller

Analog Intergrations 

AIC1573

Layout Considerations

Any inductance in the switched current path gener-

ates a large voltage spike during the switching in-

terval. The voltage spikes can degrade efficiency,

radiate noise into the circuit, and lead to device

over-voltage stress. Careful component selection

and tight layout of critical components, and short,

wide metal trace minimize the voltage spike.

A ground plane should be used. Locate the input

capacitors (CIN) close to the power switches.

Minimize the loop formed by CIN, the upper

MOSFET (Q1) and the lower MOSFET (Q2) as

possible. Connections should be as wide as short

as possible to minimize loop inductance.

The connection between Q1, Q2 and output induc-

tor should be as wide as short as practical. Since

this connection has fast voltage transitions will ea-

sily induce EMI.

The output capacitor (COUT) should be located as

close the load as possible. Because minimize the

transient load magnitude for high slew rate requires

low inductance and resistance in circuit board

The AIC1573 is best placed over a quiet ground

plane area. The GND pin should be connected to

the groundside of the output capacitors. Under no

circumstances should GND be returned to a ground

inside the CIN, Q1, Q2 loop. The GND and PGND

pins should be shorted right at the IC. This help to

minimize internal ground disturbances in the IC and

prevents differences in ground potential from dis-

rupting internal circuit operation.

The wiring traces from the control IC to the MOS-

FET gate and source should be sized to carry 1A

current. The traces for OUT2 need only be sized

for 0.5A. Locate COUT2 close to the AIC1573.

The Vcc pin should be decoupled directly to GND

by a 2.2µF ceramic capacitor, trace lengths

should be as short as possible.

A multi-layer-printed circuit board is recommended.

Figure 11 shows the connections of the critical

components in the converter. The CIN and COUT

could each represent numerous physical capacitors.

Dedicate one solid layer for a ground plane and

make all critical component ground connections

with vias to this layer.

PWM Output Capacitors

The load transient for the microprocessor core re-

quires high quality capacitors to supply the high

slew rate (di/dt) current demand.

The ESR (equivalent series resistance) and ESL

(equivalent series inductance) parameters rather

than actual capacitance determine the buck ca-

pacitor values. For a given transient load magnitude,

the output voltage transient change due to the out-

put capacitor can be note by the following equation:

∆VOUT = ESR × ∆IOUT + ESL × ∆IOUT

∆T ,

∆IOUT is transient load current step.

where

After the initial transient, the ESL dependent term

drops off. Because the strong relationship between

output capacitor ESR and output load transient, the

output capacitor is usually chosen for ESR, not for

capacitance value. A capacitor with suitable ESR

will usually have a larger capacitance value than is

needed for energy storage.

A common way to lower ESR and raise ripple cur-

rent capability is to parallel several capacitors. In

most case, multiple electrolytic capacitors of small

case size are better than a single large case ca-

pacitor.

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