AIC1573 查看數據表（PDF） - Analog Intergrations

零件编号

产品描述 (功能)

比赛名单

AIC1573

5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller

Analog Intergrations 

AIC1573

is because the gate drive applied to the upper

MOSFET is different than the lower MOSFET.

Logic level MOSFETs should be selected based on

on-resistance considerations, RDS(ON) should be

chosen base on input and output voltage, allowable

power dissipation and maximum required output

current. Power dissipation should be calculated

based primarily on required efficiency or allowable

thermal dissipation.

Rectifier Schottky diode is a clamp that prevent the

loss parasitic MOSFET body diode from conducting

during the dead time between the turn off of the

lower MOSFET and the turn on of the upper

MOSFET. The diode’s rated reverse breakdown

voltage must be greater than twice the maximum

input voltage.

Linear Controller MOSFET Selection

The power dissipated in a linear regulator is:

PLINEAR = IOUT × (V IN − VOUT )

Select a package and heatsink that maintains junc-

tion temperature below the maximum rating while

operation at the highest expected ambient tempera-

ture.

Linear Output Capacitor

The output capacitors for the linear regulator and

linear controller provide dynamic load current. The

linear controller uses dominant pole compensation

integrated in the error amplifier and is insensitive to

output capacitor selection. COUT3 and COUT4

should be selected for transient load regulation. The

output capacitor for the linear regulator provides

loop stability.

PWM Feedback Analysis

∆VOSC

VDAC

VEA

ERROR AMP.

PWM COMP.

Compensation

Networks

VIN

Q1

LO

+

CO

Q2

RESR

VOUT

Modulation

Gain

Fig 20. Control Loop

The compensation network consists of the error

amplifier and built in compensation networks. The

goal of the compensation network is to provide for

fast response and adequate phase margin. Phase

Margin is the difference between the closed loop

phase at 0dB and 180 degree.

Closed Loop Gain(dB) = Modulation Gain(dB) +

Compensation Gain (dB)

Modulation Gain(dB)

≈

20

log

VIN

∆VOSC



+

10

log1

+



F

FESR

 2





18

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