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AN209

Using Terminator Technology in Stratix & Stratix GX Devices

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AN 209: Using Terminator Technology in Stratix & Stratix GX Devices

Power Analysis

Terminator technology on-chip termination resistors increase the total

current draw of the device. This increase in current draw occurs because

the termination circuitry, which is normally external to the device, is now

a part of the device. Make sure the device’s current consumption in a

design does not exceed any device limits. You must ensure that no more

than 200 mA (Flip Chip packages) is consumed for any ten consecutive

I/O pins (excluding VCC and GND pins). The Altera® Quartus® II software

automatically performs these calculations during compilation. If the pin

assignments do not comply with these conditions, the Quartus II software

generates an error message during design compilation.

Table 4 lists the DC current draw when using on-chip series termination

for single-ended I/O standards.

Table 4. DC Current Draw for On-Chip Series Termination

Bank I/O Standard Selected by

Terminator Technology

LVTTL

LVCMOS

SSTL-2 class I

SSTL-2 class II

SSTL-3 class I

SSTL-3 class II

DC Current Draw per

Pin for Series

Termination

(Ipin in mA) (1)

0

0

10

23

11

24

VCCIO (V)

1.8, 2.5, 3.3

1.8, 2.5, 3.3

2.5

2.5

3.3

3.3

Note to Table 4:

(1) Ipin is the DC current drawn per pin.

Altera Corporation

7

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