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AN209

Using Terminator Technology in Stratix & Stratix GX Devices

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AN 209: Using Terminator Technology in Stratix & Stratix GX Devices

When using bidirectional pins, the total DC current draw by Terminator

technology on-chip termination resistors is different than the values listed

in Table 5. Table 6 lists the DC current draw values for bidirectional pins.

Table 6. DC Current Draw for On-Chip Series-Parallel Termination (Bidirectional Pins) Note (1)

Bank I/O Standard

Selected by Terminator

Technology

GTL

GTL+

SSTL-3 class I

SSTL-3 class II

SSTL-2 class I

SSTL-2 class II

CTT

HSTL class I

HSTL class II

DC Current Draw per Pin for Series & Parallel Termination

(Ipin in mA) (2)

RS

RT1 (3)

RT2 (3)

N/A

40

40

N/A

34

34

11

N/A

25

24

N/A

37

10

N/A

19

23

N/A

25

N/A

N/A (4)

27

N/A

N/A (4)

16

N/A

20

20

VCCIO (V)

3.3

3.3

3.3

3.3

2.5

2.5

3.3

1.5

1.5

Notes to Table 6:

(1) There are no current limitations for 1.5- and 1.8-V VCCIO I/O standards.

(2) Ipin is the DC current drawn per pin.

(3) RT1 and RT2 are the parallel termination resistors for the voltage referenced I/O standards. RT1 is the parallel

termination resistor next to output buffer and RT2 is the parallel termination resistor next to input buffer.

(4) The CTT output buffer and HSTL class I output buffer do not draw any current due to the on-chip termination

resistor for single-ended I/O pins, but they will still draw 8 mA as specified in the corresponding JEDEC

specifications.

Altera Corporation

9

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