CY7C143-35JI 查看數據表（PDF） - Cypress Semiconductor

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CY7C143-35JI

2K x 16 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port) [23, 28]

Either Port

tWC

ADDRESS

CE

R/W

tSCE

tAW

tSA

tPWE

DATAIN

DATAOUT

Busy Timing Diagram No. 1 (CE Arbitration)

CEL Valid First:

ADDRESS L,R

tHZWE

ADDRESS MATCH

tHA

tSD

tHD

DATA VALID

tLZWE

HIGH IMPEDANCE

CEL

CER

BUSYR

tPS

tBLC

tBHC

CER Valid First:

CY7C133

CY7C143

ADDRESS L,R

ADDRESS MATCH

CER

tPS

CEL

BUSYL

tBLC

tBHC

Note:

28. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

Document #: 38-06036 Rev. *B

Page 10 of 13

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