NM24W02 查看數據表（PDF） - Fairchild Semiconductor
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NM24W02
Fairchild Semiconductor
NM24W02 Datasheet PDF : 14 Pages
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Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to a one. There are three basic read operations: current
address read, random read, and sequential read.
Current Address Read
Internally the NM24Wxx contains an address counter that main-
tains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to one, the
NM24Wxx issues an acknowledge and transmits the eight bit
word. The master will not acknowledge the transfer but does
generate a stop condition, and therefore the NM24Wxx discontin-
ues transmission. Refer to Figure 7 for the sequence of address,
acknowledge and data transfer.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address, R/W bit set to zero, and then the word address it is
to read. After the word address acknowledge, the master imme-
diately reissues the start condition and the slave address with the
R/W bit set to one. This will be followed by an acknowledge from
the NM24Wxx and then by the eight bit word. The master will not
acknowledge the transfer but does generate the stop condition,
and therefore the NM24Wxx discontinues transmission. Refer to
Figure 8 for the address, acknowledge and data transfer se-
quence.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24Wxx continues to output data for each acknowl-
edge received. The read operation is terminated by the master not
responding with an acknowledge or by generating a stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter 'rolls over' and the
NM24Wxx continues to output data for each acknowledge re-
ceived. Refer to Figure 9 for the address, acknowledge, and data
transfer sequence.
Current Address Read (Figure 7)
S
T
S
Bus Activity: A
SLAVE
T
Master
R ADDRESS
O
T
P
SDA Line
Random Read (Figure 8)
A
C
DATA
K
DS500074-14
S
T
Bus Activity: A
Master
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
A
SLAVE
R
ADDRESS
T
SDA Line
S
A
A
A
C
C
C
K
K
K
DATA n
S
T
O
P
DS500074-15
Sequential Read (Figure 9)
Bus Activity:
Master
SLAVE
ADDRESS
SDA Line
A
C
K
DATA n
A
A
A
C
C
C
K
K
K
DATA n +1
DATA n + 2
S
T
O
P
DATA n + x
DS500074-16
NM24Wxx Rev. C.2
10
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