NM24W02 查看數據表（PDF） - Fairchild Semiconductor

零件编号

产品描述 (功能)

比赛名单

NM24W02

2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect

Fairchild Semiconductor 

Write Operations

Byte Write

For a write operation a second address field is required which is

a word address that is comprised of eight bits and provides access

to any one of the 256 words in the selected page of memory. Upon

receipt of the word address the NM24Wxx responds with an

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the NM24Wxx

begins the internal write cycle to the nonvolatile memory. While

the internal write cycle is in progress the NM24Wxx inputs are

disabled, and the device will not respond to any requests from the

master. Refer to Figure 5 for the address, acknowledge and data

transfer sequence.

Page Write

The NM24Wxx is capable of a sixteen byte page write operation.

It is initiated in the same manner as the byte write operation; but

instead of terminating the write cycle after the first data word is

transferred, the master can transmit up to fifteen more words. After

the receipt of each word, the NM24Wxx will respond with an

acknowledge.

After the receipt of each word, the internal address counter

increments to the next address and the next SDA data is accepted.

If the master should transmit more than sixteen words prior to

generating the stop condition, the address counter will 'roll over'

and the previously written data will be overwritten. As with the byte

write operation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 6 for the address, acknowl-

edge, and data transfer sequence.

Acknowledge Polling

Once the stop condition is issued to indicate the end of the host’s

write operation the NM24Wxx initiates the internal write cycle.

ACK polling can be initiated immediately. This involves issuing the

start condition followed by the slave address for a write operation.

If the NM24Wxx is still busy with the write operation no ACK will

be returned. If the NM24Wxx has completed the write operation an

ACK will be returned and the host can then proceed with the next

read or write operation.

Write Protection

Programming of the memory will not take place if the WP pin of the

NM24Wxx is connected to VCC. The NM24Wxx will accept slave

and word addresses; but if the memory accessed is write pro-

tected by the WP pin, the NM24Wxx will not generate an acknowl-

edge after the first byte of data has been received, and thus the

program cycle will not be started when the stop condition is

asserted.

Byte Write (Figure 5)

Bus Activity:

Master

S

T

A

SLAVE

R ADDRESS

T

WORD

ADDRESS

S

T

DATA

O

P

SDA Line

Bus Activity:

NM24Wxx

A

A

A

C

C

C

K

K

K

DS500074-12

Page Write (Figure 6)

Bus Activity:

Master

S

T

A

SLAVE

R ADDRESS

T

SDA Line

Bus Activity:

NM24Wxx

BYTE ADDRESS (n)

A

A

C

C

K

K

DATA n

DATA n + 1

S

T

DATA n + 15

O

P

A

A

A

C

C

C

K

K

K

DS500074-13

NM24Wxx Rev. C.2

9

www.fairchildsemi.com

Share Link: