APW7067N 查看數據表（PDF） - Anpec Electronics

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APW7067N

Synchronous Buck PWM and Linear Controller

Anpec Electronics 

APW7067N

Layout Consideration

In any high switching frequency converter, a correct

layout is important to ensure proper operation of the

regulator. With power devices switching at 300KHz or

above, the resulting current transient will cause voltage

spike across the interconnecting impedance and parasitic

circuit elements. As an example, consider the turn-off

transition of the PWM MOSFET. Before turn-off, the

MOSFET is carrying the full load current. During turn-off,

current stops flowing in the MOSFET and is free-wheeling

by the lower MOSFET and parasitic diode. Any parasitic

inductance of the circuit generates a large voltage spike

during the switching interval. In general, using short, wide

printed circuit traces should minimize interconnecting

impedances and the magnitude of voltage spike. And

signal and power grounds are to be kept separate

till combined using ground plane construction or single

point grounding. Figure 11. illustrates the layout, with bold

lines indicating high current paths; these traces must be

short and wide. Components along the bold lines should

be placed lose together. Below is a checklist for your

layout:

- The metal plate of the bottom of the packages

(QFN-16) must be soldered to the PCB and connected

to the GND plane on the backside through several

thermal vias.

- Keep the switching nodes (UGATE, LGATE and

PHASE) away from sensitive small signal nodes

since these nodes are fast moving signals. Therefore,

keep traces to these nodes as short as possible.

- The traces from the gate drivers to the MOSFETs

(UG, LG, DRIVE) should be short and wide.

- Place the source of the high-side MOSFET and the

drain of the low-side MOSFET as close as possible.

Minimizing the impedance with wide layout plane

between the two pads reduces the voltage bounce of

the node.

- Decoupling capacitor, compensation component,

the resistor dividers and boot capacitors should

be close their pins. (For example, place the

decoupling ceramic capacitor near the drain of

the high-side MOSFET as close as possible. The

bulk capacitors are also placed near the drain).

- The input capacitor should be near the drain of the

upper MOSFET; the output capacitor should be near

the loads. The input capacitor GND should be close

to the output capacitor GND and the lower MOSFET

GND.

- The drain of the MOSFETs (VIN1 and PHASE nodes)

should be a large plane for heat sinking.

VIN2

VOUT2

L

O

A

D

APW7067N

DRIVE

FBL

VCC12

BOOT

UGATE

PHASE

LGATE

VIN1

L

O

A

D

VOUT1

Figure 11. Layout Guidelines

Copyright © ANPEC Electronics Corp.

18

Rev. A.3 - Mar., 2008

www.anpec.com.tw

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