BS616LV4020 查看數據表（PDF） - Brilliance Semiconductor
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BS616LV4020
Brilliance Semiconductor
BS616LV4020 Datasheet PDF : 12 Pages
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BSI
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269 Ω
3.3V
OUTPUT
1269 Ω
INCLUDING
JIG AND
SCOPE
100PF
1404 Ω
INCLUDING
JIG AND
SCOPE
5PF
1404 Ω
FIGURE 1A
OUTPUT
THEVENIN EQUIVALENT
667 Ω
FIGURE 1B
1.73V
Vcc
GND
ALL INPUT PULSES
10%
→
90% 90%
←
→
FIGURE 2
10%
← 5ns
BS616LV4020
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC , Vcc=3.0V)
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2LQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
E1HQZ
t
BDO
t
GHQZ
t
AXQX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t (1)
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
BS616LV4020-70
MIN. TYP. MAX.
Read Cycle Time
70
Address Access Time
70
Chip Select Access Time
(CE1)
70
Chip Select Access Time
(CE2)
70
Data Byte Control Access Time (LB,UB)
35
Output Enable to Output Valid
35
Chip Select to Output Low Z
(CE2,CE1) 10
Data Byte Control to Output Low Z (LB,UB) 10
Output Enable to Output in Low Z
10
Chip Deselect to Output in High Z (CE2,CE1) 0
35
Data Byte Control to Output High Z (LB,UB) 0
35
Output Disable to Output in High Z
0
30
Output Disable to Output Address Change
10
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
BS616LV4020-10
MIN. TYP. MAX.
100
100
100
100
50
50
15
15
15
0
40
0
40
0
35
15
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV4020
6
Revision 2.3
April 2002
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