MOSEL VITELIC
V54C333322V
AC Characteristics (1,2,3)
TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-5
-55
-6
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Unit
Clock and Clock Enable
1 tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
5
–
5.5
–
6
–
ns
10
–
10
–
10
–
ns
2 tCK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
200
–
200
–
166
MHz
–
100
–
100
–
100
MHz
3 tAC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
‘
–
5
–
5.5
6
ns
2
–
7
–
7
7
ns
3
4 tCH
Clock High Pulse Width
5 tCL
Clock Low Pulse Width
6 tT
Transition time
Setup and Hold Times
2.5
–
2.5
–
2.5
–
ns
2.5
–
2.5
–
2.5
–
ns
1
10
1
10
1
10
ns
7 tCS
Command Setup Time
8 tAS
Address Setup Time
9 tDS
Data In Setup Time
10 tCKS
CKE Setup Time
11 tCH
Command Hold Time
12 tAH
Address Hold Time
13 tDH
Data In Hold Time
14 tCKH
CKE Hold Time
Common Parameters
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
ns
4
ns
4
ns
4
ns
4
ns
4
ns
4
ns
4
ns
4
15 tRCD
Row to Column Delay Time
15
–
16
–
16
–
ns
5
16 tRAS
Row Active Time
40
100K
45
100K
48
100K
ns
5
17 tRC
Row Cycle Time
60
–
63
–
66
–
ns
5
18 tRP
Row Precharge Time
15
–
17
–
18
–
ns
5
19 tRRD
Activate(a) to Activate(b) Command
10
–
11
–
12
–
ns
5
period
20 tCCD
CAS(a) to CAS(b) Command period
1
–
1
–
1
–
CLK
21 tRCS
Mode Register Set-up time
10
–
11
–
12
–
ns
22 tSB
Power Down Mode Entry Time
0
5
0
5.5
0
6
ns
Refresh Cycle
23 tREF
24 tSREX
Refresh Period (2048 cycles)
Self Refresh Exit Time
–
32
–
32
–
32
ms
2 CLK + tRC
6
V54C333322V Rev. 2.0 May 2000
10