V54C333322V 查看數據表（PDF） - Mosel Vitelic Corporation

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V54C333322V

200/183/166 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 1M X 32 SDRAM 2 BANKS X 512Kbit X 32

Mosel Vitelic Corporation  

MOSEL VITELIC

Signal Pin Description

Pin

CLK

CKE

Name

Clock Input

Clock Enable

CS

RAS

CAS

WE

A0-A10

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Address

BA

Bank Select

DQ0-DQ31

DQMi

VDD/VSS

VDDQ/VSSQ

NC

Data Input/Output

Data Input/Output Mask

Power Supply/Ground

Data Output Power/Ground

No Connection

V54C333322V

Input Function

System clock input. Active on the positive rising edge to sample all inputs

Activates the CLK signal when high and deactivates the CLK when low.

CKE low initiates the power down mode, suspend mode, or the self re-

fresh mode

Disables or enables device operation by masking or enabling all inputs

except CLK, CKE and DQMi

Latches row addresses on the positive edge of CLK with RAS low. En-

ables row access & precharge

Latches column addresses on the positive edge of CLK with CAS low.

Enables column access

Enables write operation

During a bank activate command, A0-A10 defines the row address.

During a read or write command, A0-A7 defines the column address. In

addition to the column address A8 is used to invoke auto precharge BA

define the bank to be precharged. A8 is low, auto precharge is disabled

during a precharge cycle, If A8 is high, both bank will be precharged, if

A8 is low, the BA is used to decide which bank to precharge

Selects which bank to activate. BA low select bank A and high selects

bank B

Data inputs/output are multiplexed on the same pins

Makes data output Hi-Z. Blocks data input when DQM is active

Power Supply. +3.3V ± 0.3V/ground

Provides isolated power/ground to DQs for improved noise immunity

V54C333322V Rev. 2.0 May 2000

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