SAB-C505C-4E 查看數據表（PDF） - Infineon Technologies

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比赛名单

SAB-C505C-4E

8-bit Single-chip Microcontroller

Infineon Technologies 

C505 / C505C

C505A / C505CA

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the

RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the

oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting

the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries.

a)

VDD

+

C505

C505C

C505A

C505CA

RESET

b)

C505

C505C

C505A

C505CA

RESET

&

c)

VDD

VDD

+

C505

C505C

C505A

C505CA

RESET

Figure 6

Reset Circuitries

Data Sheet

14

08.00

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