C505 / C505C
C505A / C505CA
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)
(Operating Conditions apply)
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
ALE pulse width
Address setup to ALE
Address hold after ALE
ALE to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
Symbol
Limit Values
Unit
16-MHz clock
Variable Clock
Duty Cycle 1/CLP= 2 MHz to 16 MHz
0.4 to 0.6
min. max. min.
max.
tLHLL
48
–
CLP - 15 –
ns
tAVLL
10
–
TCLHmin -15 –
ns
tLLAX
10
–
TCLHmin -15 –
ns
tLLIV
–
75 –
2 CLP - 50 ns
tLLPL
10
–
TCLLmin -15 –
ns
tPLPH
73
–
CLP+
–
ns
TCLHmin -15
tPLIV
–
38 –
CLP+
ns
TCLHmin- 50
tPXIX
0
–
0
–
ns
t *)
PXIZ
–
15 –
TCLLmin -10 ns
t *)
PXAV
20
–
TCLLmin - 5 –
ns
tAVIV
–
95 –
2 CLP + ns
TCLHmin -55
tAZPL
-5
–
-5
–
ns
*) Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Data Sheet
68
08.00