CMX625 查看數據表（PDF） - CML Microsystems Plc
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CMX625 Datasheet PDF : 34 Pages
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ISDN TA POTS Interface
CMX625
Codec Channel Input/Output Select
IC Channel Bus Reversal
(IOM Control Register
Bit 4)
Codec Channel Select
(IOM Control Register,
Bits 7 and 6)
Codec
Data
From
0
00
B1, DD
Normal
0
01
B2, DD
0
10
IC1, DD
0
11
IC2, DD
1
00
B1, DD
Reverse
1
01
B2, DD
1
10
IC1, DU
1
11
IC2, DU
Codec
Data
To
B1, DU
B2, DU
IC1, DU
IC2, DU
B1, DU
B2, DU
IC1, DD
IC2, DD
In Terminal mode (TE) it may also be necessary to transmit on the Data Downstream (DD) pin and receive
on the Data Upstream (DU) pin during the IC1 and IC2 time slots. This can be achieved by selecting bus
reversal and allows use of the CMX625 with post processing devices, such as speech scramblers, that are
IOM-2 compliant. Bus Reversal is enabled when bit 4 of the IOM Control Register is set to ‘1’ and
programming the appropriate Codec Channel Select bits 6 and 7 of the IOM Control Register. When bus
reversal is active, the master device and any other devices capable of bus reversal, are prohibited from
broadcasting in the active IC channel.
Local analogue codec loopback is enabled when bit 5 of the CODEC CONTROL Register is set to ‘1’.
This internally connects the DAC output to the ADC input (the connection to the Rx Amp is broken). Data
is loaded and read via the IOM-2 bus using the channels shown in the above table.
1.5.7 Rx Input Amplifier
This amplifier, with suitable external components, is used for adjusting the received signal to the correct
amplitude for the DTMF decoder and the PCM analogue-to-digital converter. See Figure 2 Recommended
External Components.
1.5.8 Tx Output Buffer
This buffer is enabled by bit 7 of the SETUP register. With suitable external components it can be used
for filtering and impedance matching. See Figure 2 Recommended External Components.
1.5.9 Tone/FSK Encoder and Tone Encoder
These blocks are enabled or disabled by bit 6 of the SETUP register. When bit 5 of the MODE Register is
set to ‘1’ then these blocks generate FSK signals as determined by bit 0 of the SETUP Register and the Tx
data bits from the UART block, as shown in the table below:
SETUP Register
Bit 0
0
1
Tone/FSK Generator
V23 1200bps FSK
Bell 202 1200bps FSK
FSK Signal Frequency
‘0’ (Space)
2100Hz
2200Hz
FSK Signal Frequency
‘1’ (Mark)
1300Hz
1200Hz
When bit 5 of the MODE Register is set to ‘0’, these blocks generate single or dual tones from the range
shown in the tables on the following pages. Bit 6 of the MODE Register is then used to enable or disable
the block’s output to the Tx Signal Control, RING and TONEFSK outputs. There are four tone fields
addressed by bits 0 and 1 of the MODE Register.
2001 Consumer Microcircuits Limited
14
D/625/2
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