CMX649 查看數據表（PDF） - CML Microsystems Plc

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CMX649

ADM Codec

CML Microsystems Plc 

ADM Codec

CMX649

5. General Description

The CMX649 encodes and decodes analog audio signals to/from ADM, Linear PCM, µ-law PCM or A-law

PCM. It has programmable clock dividers that enable it to use a range of 4-16 MHz crystal clocks and to

sample the data over a large range of data rates. Programmable current sources for on-chip op-amps

enable the overall power consumption to be optimised for any given supply voltage and clocking scheme,

thus achieving extremely low working power levels.

Anti-Alias Image filters and gain controls are fully programmable. All the time constants and other

parameters of the ADM can be programmed for optimum performance.

The CMX649 also includes a Microphone Amplifier, Data Clock Recovery, Data Scrambler/De-Scrambler

and Voice Activity Detector (VAD) circuits.

All of these parameters are controlled via C-BUS.

5.1 Block Descriptions

The CMX649 contains a full duplex speech codec supporting common Adaptive Delta Modulation (ADM)

and non-linear PCM coding algorithms. In addition, it supports linear PCM coding for DSP interface

applications. This codec offers simple interface and application, yet is configurable to support a wide

variety of speech quantisation systems.

5.1.1 ADM Coding Engine

ADM is a differential waveform coding technique predominantly applied to speech. Figure 3 illustrates the

ADM encoder employed. The device is for speech quantising applications and is based on popular

Continuously Variable Slope Delta (CVSD) encoder approaches, with optional modifications and

improvements configurable through the ENCODE and DECODE ADM CONTROL Registers ($E1 and

$D1). Optional second order integration in the feedback loop provides improved speech quality at a

given bit rate or similar quality at a lower bit rate. Toll quality is achieved at bit rates much lower than for

PCM. The decoder is embedded in the encoder, as is the case with most differential encoders. Note the

symmetry between the encoder and decoder of Figures 3 and 4 respectively. The signal flows for ADM

are shown in bold.

INPUT

+

-

ENCODER FEEDBACK

PCM

OUTPUT

REG $E6

PCM TO ADM TRANSCODE FEEDBACK

OFFSET NULLING

REGS $E3 & $E5

+

ENCODE

SETUP

REG $E0

ADM CTL

REG $E1

ADM

INPUT

REG $E8

DELAY

REGISTER

PROGRAMMABLE

1st

2nd

x

STEP SIZE

CONTROL

ESTIMATOR INTEGRATORS

PCM

INPUT

REG $E7

LINEAR

PCM IN

LINEAR

PCM OUT

Figure 3 ADM Encoding

ADM

OUTPUT

REG $EA

ADM OUT

© 2003 CML Microsystems Plc

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