CMX882 查看數據表（PDF） - CML Microsystems Plc
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CMX882 Datasheet PDF : 70 Pages
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FRS Signalling Processor
CMX882
AC Parameters
Notes
CLOCK/XTAL Input
'High' pulse width
31
'Low' pulse width
31
Input impedance (at 18.432MHz)
Powered-up
Resistance
Capacitance
Powered-down
Resistance
Capacitance
Clock frequency
Clock stability/accuracy
Clock start up (from power-save)
CLOCK_OUT Output
CLOCK/XTAL input to CLOCK_OUT timing:
(in high to out high)
32
(in low to out low)
32
'High' pulse width
33
'Low' pulse width
33
VBIAS
Start up time (from power-save)
Microphone, Input_2 and Disc Inputs
(MIC, INPUT_2, DISC)
Input impedance
34
Input signal range
35
Load resistance (pin 12, 14 and 16)
Amplifier open loop voltage gain
(I/P = 1mV rms at 100Hz)
Unity gain bandwidth
Programmable Input Gain Stage
36
Gain (at 0dB)
Cumulative Gain Error
(wrt attenuation at 0dB)
Min.
21
21
22
22
10
80
−0.5
−1.0
Typ.
150
20
300
20
18.432
400
15
15
27.13
27.13
30
1
60
1.0
0
Max.
Unit
±100
ns
ns
kΩ
pF
kΩ
pF
MHz
ppm
ms
ns
ns
33
ns
33
ns
ms
MΩ
90
%VDD
kΩ
dB
MHz
0.5
dB
1.0
dB
Notes: 31
32
33
34
35
36
Timing for an external input to the CLOCK/XTAL pin.
CLOCK/XTAL input driven by external source.
18.432MHz XTAL fitted.
With no external components connected
After multiplying by gain of input circuit, with external components connected.
Gain applied to signal at output of buffer amplifier, pin 12, 14 or 16
2004 CML Microsystems Plc
61
D/882/7
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