CDB43L22 查看數據表（PDF） - Cirrus Logic

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CDB43L22

Low Power, Stereo DAC w/Headphone & Speaker Amps

Cirrus Logic 

Confidential Draft

3/4/10

CS43L22

11. DIGITAL FILTER PLOTS ................................................................................................................... 63

12. PARAMETER DEFINITIONS .............................................................................................................. 64

13. PACKAGE DIMENSIONS .................................................................................................................. 65

THERMAL CHARACTERISTICS ......................................................................................................... 65

14. ORDERING INFORMATION .............................................................................................................. 66

15. REFERENCES .................................................................................................................................... 66

16. REVISION HISTORY .......................................................................................................................... 66

LIST OF FIGURES

Figure 1. Typical Connection Diagram ........................................................................................................ 9

Figure 2. Headphone Output Test Load .................................................................................................... 14

Figure 3. Serial Audio Interface Timing ..................................................................................................... 16

Figure 4. Control Port Timing - I²C ............................................................................................................ 17

Figure 5. DSP Engine Signal Flow ............................................................................................................ 21

Figure 6. Beep Configuration Options ....................................................................................................... 22

Figure 7. Peak Detect & Limiter ................................................................................................................ 23

Figure 8. Analog Passthrough Signal Flow ............................................................................................... 24

Figure 9. Analog Outputs .......................................................................................................................... 25

Figure 10. PWM Output Stage .................................................................................................................. 26

Figure 11. Battery Compensation ............................................................................................................. 28

Figure 12. I²S Format ................................................................................................................................ 30

Figure 13. Left-Justified Format ................................................................................................................ 30

Figure 14. Right-Justified Format\ ............................................................................................................. 30

Figure 15. DSP Mode Format) .................................................................................................................. 31

Figure 16. Control Port Timing, I²C Write .................................................................................................. 33

Figure 17. Control Port Timing, I²C Read .................................................................................................. 33

Figure 18. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) ................................................... 59

Figure 19. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) ................................................... 59

Figure 20. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) ................................................... 60

Figure 21. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) ................................................... 60

Figure 22. Passband Ripple ...................................................................................................................... 63

Figure 23. Stopband .................................................................................................................................. 63

Figure 24. DAC Transition Band ............................................................................................................... 63

Figure 25. Transition Band (Detail) ........................................................................................................... 63

6

DS792F2

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