CDB43L22 查看數據表（PDF） - Cirrus Logic
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CDB43L22 Datasheet PDF : 66 Pages
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Confidential Draft
3/4/10
2. TYPICAL CONNECTION DIAGRAM
+1.8 V to +2.5 V
1 µF
0.1 µF
0.1 µF
0.1 µF 1 µF
CS43L22
+1.8 V to +2.5 V
See Note 4
VD
VA
+VHP
47 kΩ
Line Level Out
Left & Right
Note 1
1 µF **
Note 2
1 µF **
FLYP
FLYN
-VHPFILT
0.022 µF
HP/LINE_OUTB
51.1 Ω
HP/LINE_OUTA
51.1 Ω
0.022 µF
SPKR/HP
CS43L22
VP
0.1 µF
Headphone Out
Left & Right
+1.6 V to
10 µF +5 V Stereo Speakers
SPKR_OUTA+
SPKR_OUTA-
VP
0.1 µF
Digital Audio
Processor
MCLK
SCLK
LRCK
SDIN
RESET
SCL
SDA
AD0
+1.8 V to +3.3 V
2 kΩ
2 kΩ
VL
0.1 µF
Notes:
1. Recommended values for the default charge pump switching
frequency. The required capacitance follows an inverse
relationship with the charge pump’s switching frequency. When
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the
capacitance must increase.
2. Larger capacitance reduces the ripple on the internal
amplifier’s supply. This may reduce the distortion at higher
output power levels.
3. Additional bulk capacitance may be added to improve PSRR
at low frequencies.
4. Series resistance in the path of the power supplies must be
avoided. Any voltage drop on VHP will directly impact the
negative charge pump supply (-VHPFILT) and clip the audio
output.
TSTO
TSTO
SPKR_OUTB+
SPKR_OUTB-
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
AIN4A
AIN4B
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
**
1 µF
**
1 µF
100 kΩ
100 kΩ
Left 1
Analog
Input 1
Right 1
**
1 µF
**
1 µF
100 kΩ
100 kΩ
Left 2
Analog
Input 2
Right 2
**
1 µF
**
1 µF
100 kΩ
100 kΩ
Left 3
Analog
Input 3
Right 3
**
1 µF
**
1 µF
100 kΩ
100 kΩ
Left 4
Analog
Input 4
Right 4
AGND
AFILTA
AFILTB
VQ
FILT+
*
150 pF
*
150 pF
Note 3
1 µF
10 µF
DGND
* Capacitors must be C0G or equivalent
** Low ESR, X7R/X5R dielectric capacitors.
Figure 1. Typical Connection Diagram
DS792F2
9
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