CS5509-ASZ(2009) 查看數據表（PDF） - Cirrus Logic
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CS5509-ASZ Datasheet PDF : 24 Pages
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CS5509
5V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%;
Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2)
Parameter
Symbol
Master Clock Frequency
Internal Oscillator XIN
External Clock fclk
Master Clock Duty Cycle
Rise Times
Any Digital Input (Note 10)
Any Digital Output
trise
Fall Time
Any Digital Input (Note 10)
Any Digital Output
tfall
Start-Up
Power-On Reset Period
(Note 11) tres
Oscillator Start-up Time
XTAL = 32.768 kHz (Note 12) tosu
Wake-up Period
(Note 13) twup
Calibration
CONV Pulse Width (CAL = 1)
(Note 14) tccw
CONV and CAL High to Start of Calibration
tscl
Start of Calibration to End of Calibration
tcal
Conversion
CONV Pulse Width
tcpw
CONV High to Start of Conversion
tscn
Set Up Time
BP/UP stable prior to DRDY falling tbus
Hold Time
BP/UP stable after DRDY falls tbuh
Start of Conversion to End of Conversion
(Note 15) tcon
Min
30.0
30
40
-
-
-
-
-
-
-
100
-
-
100
-
82/fclk
0
-
Typ
Max Unit
32.768 53.0 kHz
-
330
kHz
-
60
%
-
1.0
µs
50
-
ns
-
1.0
µs
20
-
ns
10
-
ms
500
-
ms
1800/fclk
-
s
-
-
ns
-
2/fclk+200 ns
3246/fclk
-
s
-
-
ns
-
2/fclk+200 ns
-
-
s
-
-
ns
1624/fclk
-
s
Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using
an external clock source.
13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on
reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.
4
DS125F3
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