CDB6403 查看數據表（PDF） - Cirrus Logic

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产品描述 (功能)

比赛名单

CDB6403

Echo-Cancelling Codec

Cirrus Logic 

CS6403

RESERVED2 - PIN 12Q, 18L

Must be grounded in normal operation.

RESERVED3 - PIN 5Q, 11L

Must be grounded in normal operation.

RESERVED4 - PIN 16Q, 22L

Must be grounded in normal operation.

RESERVED5 - PIN 36Q, 42L

Must be grounded in normal operation.

RESERVED6 - PIN 17Q, 23L

Must be grounded in normal operation.

Mode Control

CONFIG - Configuration-control input, PIN 11Q, 17L

CONFIG is used in conjunction with other configuration-control pins to control operating mode

(see Table 2). Serial data is 16-bits long in Mode 2 if CONFIG is high, 8-bits if CONFIG is

low.

SCLK_RATE0 - SCLK frequency control, PIN 29Q, 35L

Used in conjunction with SCLK_RATE1 to set the SCLK frequency when the CS6403 is a

timing slave. Possible frequencies are 2.048 MHz, 1.024 MHz, and 256 kHz, for

SCLK_RATE1:SCLK_RATE0 being 11, 10, and 00, respectively. However, if the CS6403 is a

timing master (i.e., SMASTER is high), the SCLK frequency may only be 2.048 MHz, so in

this case, SCLK_RATE0 must be high.

SCLK_RATE1 - SCLK frequency control, PIN 30Q, 36L

Used in conjunction with SCLK_RATE0 to set the SCLK frequency when the CS6403 is a

timing slave. Possible frequencies are 2.048 MHz, 1.024 MHz, and 256 kHz, for

SCLK_RATE1:SCLK_RATE0 being 11, 10, and 00, respectively. However, if the CS6403 is a

timing master (i.e., SMASTER is high), the SCLK frequency may only be 2.048 MHz, so in

this case, SCLK_RATE1 must be high.

SFRAME - SSYNC frame/pulse control, PIN 1Q, 7L

If SFRAME is high, SYNCOUT is high during serial data transactions. If SFRAME is low,

SYNCOUT is pulsed high for one SCLK period before the start of a serial-data transaction.

DS192PP6

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