CDB6403 查看數據表（PDF） - Cirrus Logic

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CDB6403

Echo-Cancelling Codec

Cirrus Logic 

CDB6403

GPIN3

By default, the CS6403 runs with an internal

26dB gain stage on MICIN. This feature is not

desirable in some applications and so GPIN3 is

provided to disable this feature. If the applica-

tion you wish to implement needs the additional

26dB MICIN gain, set GPIN3 to ground, other-

wise set it high.

The 26dB disable/enable status is read only at

reset. If the state of GPIN3 is toggled anytime

after reset, the CS6403 MICIN will be muted.

Mode 1 Setup

To configure the CDB6403 for Mode 1 opera-

tion, the DIP switches should be set as follows

(* indicates a non-mode specific option):

Switch State

Details

SFRAME

ON*

Pulse-type SYNC

(frame-type should work, also)

SMASTER OFF CS6403 must source SCLK

SCLK_RATE1

OFF

Mode 1 requires 2.048MHz

SCLK to be generated

SCLK_RATE0

OFF

Mode 1 requires 2.048MHz

SCLK to be generated

CONFIG

ON Select Mode 1

UALAW

OFF*

Select µ-law companding

law should work, also)

(A-

GPIN3

ON*

Enable MIC gain

(may not be necessary)

CLK_SEL

ON Enable on-chip PLL

Connect the far-end signals to FE_IN and

FE_OUT, and the near-end signals to MICIN

and SPKROUT.

Mode 2 Setup

To configure the CDB6403 for Mode 2 opera-

tion, the DIP switches should be set as follows

(* indicates a non-mode specific option):

Switch State

Details

SFRAME

ON Pulse-type SYNC

SMASTER

ON CS6403 must slave to SCLK

SCLK_RATE1

OFF*

Varies based on SCLK

presented to SSI

SCLK_RATE0

OFF*

Varies based on SCLK

presented to SSI

CONFIG

OFF Select Mode 2

UALAW

OFF*

Since data is linear in Mode

2, this does not apply

GPIN3

ON*

Enable MIC gain

(may not be necessary)

CLK_SEL

ON Enable on-chip PLL

Connect the near-end signals to MICIN and

SPKROUT. The far-end signals should be provided

through the SSI. A DSP serial port is ideal for this.

Setting the CDB6403 up to interface to

line-level signals

Much audio equipment is designed to expect

line-level signals. These signals are a maximum

of 2Vrms or approximately 5.6Vpp. The

CDB6403 is not configured to handle signals of

this amplitude by default, but can be easily

modified to accommodate it.

To configure the far-end input, FE_IN, to accom-

modate 5.6Vpp, we have to scale down the

signal to 3.15Vpp (full scale input of the

MC145480). This is easily accomplished by

merely changing R2 and R9 to 5.6kΩ, which

will change the gain of the differential amplifier

at the input to the MC145480 to 0.56 (3.15/5.6).

DS192DB3

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