CXP86609 查看數據表（PDF） - Sony Semiconductor
零件编号
产品描述 (功能)
比赛名单
CXP86609 Datasheet PDF : 20 Pages
| |||
CXP86609/86613/86617
Pin
PE0/TO/ADJ
1 pin
Circuit format
Port E
Internal reset signal
Port E data
00
"1" after reset
AADDJ1JT62OKK∗∗11
01 MPX
10
11
∗2
Port E function selection (upper)
Port E function selection (lower)
"00" after reset
Port E direction
"1" after reset
Data bus
RD (Port E)
∗1 ADJ signals are frequency
dividing outputs for 32kHz
oscillation frequency
IP
adjustment.
ADJ2K provides usage as
buzzer output.
∗2 Pull-up transistor approx. 150kΩ
Port E
After reset
High level
(with the
resistor of
pull-up
transistor ON
when reset)
PE1
1 pin
Port E data
"1" after reset
Port E direction
"1" after reset
Data bus
RD (Port E)
Port E
PE2/TEX/INT0
PE3/TX
PE2/
TEX/
IP
INT0
High level
IP
32kHz oscillation circuit control
"1" after reset
Schmitt input
INT0
Data bus
RD (Port E)
Data bus
RD (Port E)
Schmitt input
IP
Clock input
Oscillation
stop
Port input
PE3/
2 pins
TX
–8–
Share Link: 