CY2308 查看數據表（PDF） - Cypress Semiconductor
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CY2308 Datasheet PDF : 14 Pages
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CY2308
Switching Characteristics for Commercial Temperature Devices (continued)
Parameter[8]
t3
t3
t4
t4
Name
Rise Time[7, 8]
(–1, –2, –3, –4)
Rise Time[7, 8]
(–1H, –5H)
Fall Time[7, 8]
(–1, –2, –3, –4)
Fall Time[7, 8]
(–1, –2, –3, –4)
Test Conditions
Min Typ.
Measured between 0.8V and 2.0V,
–
–
15-pF load
Measured between 0.8V and 2.0V,
–
–
30-pF load
Measured between 0.8V and 2.0V,
–
–
30-pF load
Measured between 0.8V and 2.0V,
–
–
15-pF load
t4
Fall Time[7, 8]
Measured between 0.8V and 2.0V,
–
–
(–1H, –5H)
30-pF load
t5
Output to Output Skew on All outputs equally loaded
–
–
same Bank
(–1, –2, –3, –4)[7, 8]
Output to Output Skew (–1H, All outputs equally loaded
–5H)
–
–
Output Bank A to Output All outputs equally loaded
Bank B Skew (–1, –4, –5H)
–
–
Output Bank A to Output
Bank B Skew (–2, –3)
All outputs equally loaded
–
–
t6
Delay, REF Rising Edge to
FBK Rising Edge[7, 8]
Measured at VDD/2
–
0
t7
Device to Device Skew[7, 8] Measured at VDD/2 on the FBK pins
–
0
of devices
t8
Output Slew Rate[7, 8]
Measured between 0.8V and 2.0V on 1
–
–1H, –5H device using Test Circuit 2
tJ
Cycle to Cycle Jitter[7, 8]
Measured at 66.67 MHz, loaded
–
75
(–1, –1H, –4, –5H)
outputs,
15-pF load
Measured at 66.67 MHz, loaded
outputs,
30-pF load
–
–
Measured at 133.3 MHz, loaded
outputs,
15-pF load
–
–
tJ
Cycle to Cycle Jitter[7, 8]
Measured at 66.67 MHz, loaded
–
–
(–2, –3)
outputs
30-pF load
tLOCK
PLL Lock Time[7, 8]
Measured at 66.67 MHz, loaded
outputs
15-pF load
–
–
Stable power supply, valid clocks
–
–
presented on REF and FBK pins
Max
1.50
1.50
2.20
1.50
1.25
200
200
200
400
±250
700
200
200
100
400
400
1.0
Unit
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ps
ps
ps
ms
Document Number: 38-07146 Rev. *F
Page 5 of 14
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