CY7C1011CV33-10BVC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1011CV33-10BVC Datasheet PDF : 11 Pages
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CY7C1011CV33
AC Test Loads and Waveforms[3]
10-ns devices:
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50 Ω
1.5V
(a)
30 pF*
3.0V
GND
ALL INPUT PULSES
90%
90%
10%
10%
12-, 15-ns devices:
3.3V
OUTPUT
30 pF
R 317Ω
R2
351Ω
(b)
High-Z characteristics:
3.3V
R 317Ω
OUTPUT
5 pF
R2
351Ω
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
AC Switching Characteristics Over the Operating Range [4]
-10
-12
-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tpower[5]
VCC(typical) to the first access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low-Z
OE HIGH to High-Z[6, 7]
CE LOW to Low-Z[7]
CE HIGH to High-Z[6, 7]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
Write Cycle[8, 9]
1
1
1
µs
10
12
15
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
5
6
7
ns
3
3
3
ns
5
6
7
ns
0
0
0
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
6
6
7
ns
tWC
Write Cycle Time
10
12
15
ns
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load
shown in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05232 Rev. *B
Page 4 of 11
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