CY7C1011CV33-10BVC 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
比赛名单
CY7C1011CV33-10BVC Datasheet PDF : 11 Pages
| |||
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS
tRC
CE
OE
BHE, BLE
tACE
tDOE
tLZOE
tDBE
tLZBE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
tLZCE
tPU
50%
Write Cycle No. 1 (CE Controlled)[13, 14]
CY7C1011CV33
tHZOE
DATA VALID
tHZCE
tHZBE
HIGH
IMPEDANCE
tPD
50%
IICCCC
IISSBB
tWC
ADDRESS
CE
tSA
tSCE
WE
BHE, BLE
DATAI/O
tAW
tPWE
tBW
tSD
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
tHA
tHD
Document #: 38-05232 Rev. *B
Page 6 of 11
Share Link: 