CY7C1300A-83AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1300A-83AC Datasheet PDF : 12 Pages
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CY7C1300A
Pin Definitions
Name
I/O
Description
AX0–
Input– Synchronous Address Inputs of Port X: Do not allow address pins to float.
AX16 Synchronous
AY0–
Input– Synchronous Address Inputs of Port Y: Do not allow address pins to float.
AY16 Synchronous
WEX
Input– Read Write of Port X: WEX signal is a synchronous input that identifies whether the current loaded
Synchronous cycle is a Read or Write operation.
WEY
Input– Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current loaded cycle
Synchronous is a Read or Write operation.
PTX
Input– Pass-Through of Port X: PTX signal is a synchronous input that enables passing Port X input to Port
Synchronous Y output.
PTY
Input– Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input to Port
Synchronous X output.
OEX
Input
Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH, the
DQXx pins are in high-impedance state.
OEY
Input
Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH, the
DQYx pins are in high-impedance state.
DQX0–
DQX35
Input/ Data Inputs/Outputs of Port X: Both the data input path and data output path are registered and
Output triggered by the rising edge of CLK.
DQY0–
DQY35
Input/ Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered and
Output triggered by the rising edge of CLK.
CLK
Input– Clock: This is the clock input to this device. Except for OEX and OEY, all timing references of the address,
Synchronous data in, and all control signals for the device are made with respect to the rising edge of CLK.
CE1X
Input– Synchronous Active LOW Chip Enable Port X: CE1X is used with CE2X to enable Port X of this
Synchronous device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for Port X.
CE2X
Input– Synchronous Active HIGH Chip Enable Port X: CE2X is used with CE1X to enable Port X of this
Synchronous device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for Port X.
CE1Y
Input– Synchronous Active LOW Chip Enable Port Y: CE1Y is used with CE2Y to enable Port Y of this device.
Synchronous CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for Port Y.
CE2Y
Input– Synchronous Active HIGH Chip Enable Port Y: CE2Y is used with CE1Y to enable Port Y of this
Synchronous device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for Port Y.
VCC
Supply Power Supply: +3.3V –5% and +5%.
VSS
Ground Ground: GND.
VSS
Ground Ground: GND. No chip current flows through these pins. However, the user needs to connect GND to
these pins.
VCCQ
NC
I/O Supply Output Buffer Supply: +3.3V -5% and +5%.
–
No Connect: These signals are not internally connected. The user can connect them to VCC, VSS, or
any signal lines, or simply leave them floating.
Cycle Description Truth Table [2, 3, 4, 5, 6, 7, 8, 9]
Operation
CE1X
CE2X CE1Y CE2Y
WEX
WEY
PTX
PTY
Deselect Cycle
H
X
H
X
X
X
X
X
Deselect Cycle
X
L
X
L
X
X
X
X
Write Port X
L
H
X
X
0
X
X
X
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For Write and Pass-through operations following a Read
operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data
hold time.
5. Operation numbers 3–6 can be used in any combination.
6. Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined.
7. Operation numbers 5 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation.
8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation.
9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up
Document #: 38-05075 Rev. *C
Page 3 of 12
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