CY7C1300A-83AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1300A-83AC Datasheet PDF : 12 Pages
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CY7C1300A
Cycle Description Truth Table (continued)[2, 3, 4, 5, 6, 7, 8, 9]
Operation
Write Port Y
Pass-through from X to Y
Pass-through from Y to X
Read Port X
Read Port Y
CE1X
X
L
L
L
X
CE2X CE1Y CE2Y
WEX
WEY
PTX
PTY
X
L
H
X
0
X
X
H
L
H
X
X
0
X
H
L
H
X
X
X
0
H
X
X
1
X
1
1
X
L
H
X
1
1
1
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −55°C to +125°C
Ambient Temperature with
Power Applied.................................................... −10°C to +85°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[10] ...................................−0.5V to VCCQ + 0.5V
DC Input Voltage[10]................................−0.5V to VCCQ + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ......................................... > 1601V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature[11]
0°C to +70°C
VDD/VDDQ(12)
3.3V ± 5%
Electrical Characteristics Over the Operating Range
Paramete
r
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
IOZ
ICC
ISB
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH
Voltage[13]
Input LOW Voltage[14]
Input Load Current
Output Leakage
Current
VDD Operating Supply
Automatic CE
Power-down
Current—CMOS
Inputs
Test Conditions
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
GND ≤ VIN ≤ VDDQ
GND ≤ VIN ≤ VDDQ, Output Disabled
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected[15],
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f=0
10.0 ns cycle, MHz
12.0 ns cycle, 83 MHz
10.0 ns cycle, 100 MHz
12.0 ns cycle, 83 MHz
Min.
3.135
3.135
2.4
2.0
−0.5
−5
−5
Max.
3.465
3.465
0.4
VCC + 0.5V
0.8
5
5
500
430
140
120
Unit
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance[16]
Parameter
Description
Test Conditions
CIN
CCLK
Input capacitance
Clock input capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V,
VCCQ = 3.3V
Notes:
10. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
11. TA is the case temperature.
12. Power supply ramp up should be monotonic.
13. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
14. Undershoot: VIL ≤ –2.0V for t ≤ tKC /2.
15. “Device Deselected” means the device is in power-down mode as defined in the truth table.
16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05075 Rev. *C
Max.
Unit
8
pF
9
pF
Page 4 of 12
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