CY7C43684AV-7AC 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

比赛名单

CY7C43684AV-7AC

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644AV

CY7C43664AV

CY7C43684AV

Density

Package

CY7C43644AV

1K × 36 × 2

128 TQFP

CY7C43664AV

4K × 36 × 2

128 TQFP

CY7C43684AV

16K × 36 × 2

128 TQFP

Pin Definitions

Signal Name

A0–35

AEA

Description

Port A Data

Port A Almost

Empty Flag

AEB

Port B Almost

Empty Flag

AFA

Port A Almost

Full Flag

AFB

Port B Almost

Full Flag

B0–35

BE/FWFT

Port B Data

Big Endian/

First-Word Fall-

Through Select

BM

Bus Match

Select (Port A)

CLKA

Port A Clock

CLKB

Port B Clock

CSA

CSB

EFA/ORA

Port A Chip

Select

Port B Chip

Select

Port A Empty/

Output Ready

Flag

I/O

Function

I/O 36-bit bidirectional data port for side A.

O Programmable Almost Empty flag synchronized to CLKA. It is LOW when the

number of words in FIFO2 is less than or equal to the value in the Almost Empty A

offset register, X2.[2]

O Programmable Almost Empty flag synchronized to CLKB. It is LOW when the

number of words in FIFO1 is less than or equal to the value in the Almost Empty B

offset register, X1.[2]

O Programmable Almost Full flag synchronized to CLKA (MHz). It is LOW when the

number of empty locations in FIFO1 is less than or equal to the value in the Almost Full

A offset register, Y1.[2]

O Programmable Almost Full flag synchronized to CLKB. It is LOW when the number

of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset

register, Y2.[2]

I/O 36-bit bidirectional data port for side B.

I This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian

operation. In this case, depending on the bus size, the most significant byte or word

on Port A is transferred to Port B first for A-to-B data flow. For data flowing from port B

to Port A, the first word/byte written to Port B will come out as the most significant word/

byte on port A. On the other hand, a LOW on BE will select Little Endian operation. In

this case, the least significant byte or word on Port A is transferred to Port B first for A-

to-B data flow. Similarly, the first word/byte written into port B will come out as the least

significant word/byte on Port A for B-to-A data flow. After Master Reset, this pin selects

the timing mode. A HIGH on BE/FWFT selects CY Standard mode, a LOW selects

First-Word Fall-Through mode. Once the timing mode has been selected, the level on

this pin must be static throughout device operation.

I A HIGH on this pin enables either byte or word bus width on Port B, depending

on the state of SIZE. A LOW selects long word operation. BM works with SIZE and BE

to select the bus size and endian arrangement for Port B. The level of BM must be

static throughout device operation.

I CLKA is a continuous clock that synchronizes all data transfers through Port A

and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA

are all synchronized to the LOW-to-HIGH transition of CLKA.

I CLKB is a continuous clock that synchronizes all data transfers through Port B

and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB

are all synchronized to the LOW-to-HIGH transition of CLKB.

I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to Read or Write

on Port A. The A0–35 are in the high-impedance state when CSA is HIGH.

I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to Read or Write

on Port B. The B0–35 are in the high-impedance state when CSB is HIGH.

O This is a dual-function pin. In the CY Standard mode, the EFA function is selected.

EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA

function is selected. ORA indicates the presence of valid data on A0–35 outputs

available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of

CLKA.

Document #: 38-06025 Rev. *C

Page 4 of 37

Share Link: