CY7C43684AV-7AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C43684AV-7AC
Cypress Semiconductor
CY7C43684AV-7AC Datasheet PDF : 37 Pages
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CY7C43644AV
CY7C43664AV
CY7C43684AV
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X4AV
undergoes a complete reset by taking its associated Master
Reset (MRS1, MRS2) input LOW for at least four Port A clock
(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transi-
tions. The Master Reset inputs can switch asynchronously to
the clocks. A Master Reset initializes the internal Read and
Write pointers and forces the Full/Input Ready flag (FFA/IRA,
FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and
the Almost Full flag (AFA, AFB) HIGH. A Master Reset also
forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox
register HIGH. After a Master Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two clock cycles to begin normal
operation. A Master Reset must be performed on the FIFO
after power up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X4AV
undergoes a limited reset by taking its associated Partial
Reset (PRS1, PRS2) input LOW for at least four Port A clock
(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transi-
tions. The Partial Reset inputs can switch asynchronously to
the clocks. A Partial Reset initializes the internal Read and
Write pointers and forces the Full/Input Ready flag (FFA/IRA,
FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and
the Almost Full flag (AFA, AFB) HIGH. A Partial Reset also
forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox
register HIGH. After a Partial Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two clock cycles to begin normal
operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First Word Fall Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B. (Note that when Port B is
configured for a long word size, the Big Endian function has
no application and the BE input is a “Don’t Care.”)
Document #: 38-06025 Rev. *C
A HIGH on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big
Endian arrangement. When data is moving in the direction
from Port A to Port B, the most significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
the least significant byte (word) of the long word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port B to Port A, the byte (word) written to Port
B first will be transferred to Port A as the most significant byte
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the least significant byte (word)
of the long-word.
A LOW on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long word written to Port A will be transferred to Port B first;
the most significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port B to Port A, the byte (word) written to Port
B first will be transferred to port A as the least significant byte
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the most significant byte (word)
of the long-word.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) mode.
Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY
Standard mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal Read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT
mode. This mode uses the Output Ready function (ORA,
ORB) to indicate whether or not there is valid data at the data
outputs (A0–35 or B0–35). It also uses the Input Ready function
(IRA, IRB) to indicate whether or not the FIFO memory has any
free space for writing. In the FWFT mode, the first word written
to an empty FIFO goes directly to data outputs, no Read
request necessary. Subsequent words must be accessed by
performing a formal Read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X4AV are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see Table 3). To load a FIFO’s
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