EP9315 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

比赛名单

EP9315

Enhanced Universal Platform System-on-Chip Processor

Cirrus Logic 

EP9315

Enhanced Universal Platform SOC Processor

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these

diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached

unless specifically stated.

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to Tristate

Bus/Signal Omission

Timing Conditions

Figure 1. Timing Diagram Drawing Key

Unless specified otherwise, the following conditions are true for all timing measurements.

• TA = 0 to 70° C

• CVDD = VDD_PLL = 1.8V

• RVDD = 3.3 V

• All grounds = 0 V

• Logic 0 = 0 V, Logic 1 = 3.3 V

• Output loading = 50 pF

• Timing reference levels = 1.5 V

• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between

33 MHz and 100 MHz (92 MHz for industrial conditions).

14

©Copyright 2005 Cirrus Logic (All Rights Reserved)

DS638PP4

Share Link: