FAN5069(2005) 查看數據表（PDF） - Fairchild Semiconductor
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FAN5069 Datasheet PDF : 20 Pages
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Block Diagram
Vcc
RILIM ILIM
Internal Vcc 5.6V Max.
Shunt Reg 10μA
Current Limit
Comparator
Internal
Boot Diode
COMP
FB
Vref
Error
Amplifier
Vcc
PWM
Comparator
10μA
OSC
SS
VIN
RRAMP
R(RAMP)
EN
Ramp
Generator
Enable
Summing
Σ
Amplifier
PWM
RQ
S
Adaptive
Gate Drive
Circuit
Current
Sense
Amplifier
BOOT
CBOOT
VIN
HDRV
SW
LDRV
PGND
LO
Vout
CO
Figure 20. Block Diagram
Detailed Operation Description
FAN5069 combines a high efficiency fixed-frequency PWM con-
troller designed for single phase synchronous buck Point-Of-
Load converters with an integrated LDO controller to support
GTL type of loads. This controller is ideally suited to deliver low
voltage, high current power supplies needed in desktop comput-
ers, notebooks, workstations and servers. The controller comes
with an integrated boot diode which helps reduce component
cost and increase space savings. With this controller, the input
to the power supply can be varied from 3V to 24V and the out-
put voltage can be set to regulate at 0.8V to 15V on the switcher
output. The LDO output can be configured to regulate between
0.8V to 3V and the input to the LDO can be from 1.5V to 5V,
respectively. An internal shunt regulator at the VCC pin facilitates
the controller operation from either a 5V or 12V power source.
VCC Bias Supply
The FAN5069 is capable of operating from either a 5V or 12V
supply. The internal shunt regulator at the VCC pin is capable of
sinking 150mA of current to ensure that the controller’s internal
VCC is maintained at 5.6V Max. To operate from a 12V supply,
an external resistor must be used between the 12V supply and
the Vcc pin as shown in Figure 1.
Select a resistor such that:
■ It is rated to handle the power dissipation
■ Current sunk within the controller is minimized to prevent
temperature rise.
PWM Section
The FAN5069’s PWM controller combines the conventional volt-
age mode control and current sensing through lower MOSFET
RDS_ON to generate the PWM signals. Although this method of
current sensing is loss-less and cost effective, for more accurate
current sense requirements an optional external resistor can be
connected with the bottom MOSFET in series.
PWM Operation
Refer to Figure 20 for the PWM control mechanism. The
FAN5069 uses the summing mode method of control to gener-
ate the PWM pulses. The amplified output of the current sense
amplifier is summed with an internally generated ramp and the
combined signal is amplified and compared with the output of
the error amplifier to get the pulse width to drive the high-side
MOSFET. The sensed current from the previous cycle is used to
modulate the output of the summing block. The output of the
summing block is also compared against the voltage threshold
set by the RLIM resistor to limit the inductor current on a cycle-
by-cycle basis. The controller facilitates external compensation
for enhanced flexibility.
Initialization
When the PWM is disabled, the SW node is connected to GND
through an internal 70Ω MOSFET to slowly discharge the out-
put. As long as the PWM controller is enabled, this internal
MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high, the cir-
cuit releases SS and enables the PWM regulator. The capacitor
connected to the SS pin and GND is now charged by a 10µA
internal current source causing the voltage on the capacitor to
rise. When this voltage exceeds 1.2V, all protection circuits are
enabled. When this voltage exceeds 2.2V, the LDO output is
enabled. The input to the error amplifier at the non-inverting pin
is clamped by the voltage on the SS pin until it crosses the refer-
ence voltage.
The time it takes the PWM output to reach regulation (TRise) is
calculated using the following equation:
TRISE = 8 × 10–2 × CSS (CSS is in μf)
(EQ. 1)
FAN5069 Rev. 1.1.0
10
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