MD56V62400 查看數據表（PDF） - Oki Electric Industry

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产品描述 (功能)

比赛名单

MD56V62400

4-Bank x 4,194,304-Word x 4-Bit SYNCHRONOUS DYNAMIC RAM

Oki Electric Industry 

¡ Semiconductor

MD56V62400/H

PIN DESCRIPTION

CLK

CS

CKE

Address

A12, A13

(BA1, BA0)

RAS

CAS

WE

DQM

DQi

Fetches all inputs at the "H" edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM.

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is

deactivated. CKE should be asserted at least one cycle prior to a new command.

Row & column multiplexed.

Row address: RA0 – RA11

Column address: CA0 – CA9

Bank Access pins. These pins are dedicated to select one of 4 banks.

Functionality depends on the combination. For details, see the function truth table.

Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal.

Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal.

Data inputs/outputs are multiplexed on the same pin.

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