MD56V62400 查看數據表（PDF） - Oki Electric Industry

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MD56V62400

4-Bank x 4,194,304-Word x 4-Bit SYNCHRONOUS DYNAMIC RAM

Oki Electric Industry 

¡ Semiconductor

MD56V62400/H

AC Characteristics

Parameter

MD56V62400-10

Symbol

Min. Max.

CL = 3

10

—

Clock Cycles Time

tCC

CL = 2

15

—

Access Time from CL = 3

Clock

CL = 2

tAC

—

—

9

9

Clock "H" Pulse Time

Clock "L" Pulse Time

tCH

3

—

tCL

3

—

Input Setup Time

Input Hold Time

tSI

3

—

tHI

1

—

Output Low Impedance

Time from Clock

tOLZ

3

—

Note 1, 2

MD56V62400-12 MD56V62400H-15

Unit Note

Min. Max. Min. Max.

12

—

15

— ns

17.5

—

15

— ns

—

10

—

9

ns 3, 4

—

14

—

9

ns 3, 4

3

—

3

— ns

3

—

3

— ns

3

—

3

— ns

1.5

—

1

— ns

3

—

3

— ns

Output High Impedance

Time from Clock

tOHZ

—

8

—

10

—

8

ns

Output Hold from Clock

tOH

3

RAS Cycle Time

tRC

90

RAS Precharge Time

tRP

30

RAS Active Time

tRAS

60

RAS to CAS Delay Time

tRCD

30

Write Recovery Time

tWR

15

RAS to RAS Bank Active

Delay Time

tRRD

20

—

3

—

3

— ns 3

—

115

—

105

— ns

—

45

—

30

— ns

105

70

105

70

105 ns

—

35

—

30

— ns

—

24

—

15

— ns

—

24

—

24

— ns

Refresh Time

tREF

—

64

Power-down Exit Set-up Time tPDE tSI + 1 CLK —

Input Level Transition Time tT

CAS to CAS Delay Time (Min.) lCCD

—

3

1

Clock Disable Time from CKE lCKE

1

Data Output High Impedance

Time from DQM

lDOZ

2

—

64

tSI + 1 CLK —

—

3

1

1

2

—

64

tSI + 1 CLK —

—

3

1

1

2

ms

ns

ns

Cycle

Cycle

Cycle

Data Input Mask Time from

DQM

lDOD

0

0

0

Cycle

Data Input Time from Write

Command

lDWD

0

0

0

Cycle

Data Output High Impedance

Time from Precharge Command

lROH

2

2

2

Cycle

Active Command Input Time from Mode

Register Set Command Input (Min.)

lMRD

3

3

3

Cycle

Write Command Input Time

from Output

lOWD

2

2

2

Cycle

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