GA100NA60U
Vg G ATE SIG NAL
DEVICE UNDER TEST
CUR REN T D .U .T.
VO LTAG E IN D.U.T.
CURRENT IN D1
t0
t1 t2
Figure 17e. Macro Waveforms for Figure 17a's Test Circuit
50V
6000µF
100V
L
1 0 0 0 V Vc*
D.U.T.
0 - 480V
RL=
480V
4 X IC @25°C
Figure 18. Clamped Inductive Load Test Circuit
Figure 19. Pulsed Collector Current
Test Circuit
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