HI5780-EV 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

比赛名单

HI5780-EV

10-Bit, 80 MSPS, High Speed, Low Power D/A Converter

Intersil 

HI5780

Detailed Description

Reference

The HI5780 is a 10-bit, current out D/A converter. The DAC

can convert at 80 MSPS and runs on +5V supplies. The

HI5780 achieves its low power and high speed performance

from an advanced CMOS process. The HI5780 consumes

150mW (Maximum) and has a power down mode that only

consumes 1.25mW when in sleep mode. The HI5780 is an

excellent converter to be used for communications applica-

tions and high performance video systems.

The internal reference in the HI5780 is a 1.25V (typical)

bandgap voltage reference. The internal reference is buff-

ered by an amplifier to provide adequate drive for the current

cells. Reference Out (REFOUT) is connected to the VREF pin.

The Full Scale Output Current is controlled by the resistor

connected to IREF. The full scale output voltage, is set by the

following equation:

VO UT(Full Scale) = VREF x 16(RLOAD /RREF ).

Digital Inputs

The HI5780 is a TTL/CMOS-compatible D/A. Data is latched

by a 10-bit latch. Once latched data inputs D0 (LSB) thru D9

(MSB) are decoded to the internal current cells; the internal

latch and switching current source controls are implemented

in CMOS technology to maintain high switching speeds and

low power consumption.

Clocks and Termination

Applications

Voltage Conversion of the Output

To convert the output current of the D/A converter to a

voltage, an amplifier should be used as shown in Figure 5.

The DAC needs a 50Ω termination resistor on the IOUT pin to

ensure proper settling. The HFA1110 has an internal feed-

back resistor to compensate for high frequency operation.

The internal 10-bit register is updated on the rising edge of

the clock. Since the HI5780 clock rate can run to 80MHz, to

minimize reflections and clock noise into the part, proper ter-

mination should be used. In PCB layout clock runs should be

kept short and have a minimum of loads. To guarantee con-

sistent results from board to board, controlled impedance

PCBs should be used with a characteristic line impedance,

ZO, of 50Ω .

To terminate the clock line a shunt terminator to ground is the

most effective type at a 80 MSPS clock rate. A typical value

for termination can be determined by the equation:

RT = ZO,

for the termination resistor. For a controlled impedance

board with a ZO of 50Ω, the RT = 50Ω. Shunt termination is

best used at the receiving end of the transmission line or as

close to the HI5780 CLK pin as possible.

+5V

HI5780

DAC

21

IOUT

50Ω

21

HFA1110

4

-

+

65

8

50Ω

-5.2V

FIGURE 10. HIGH SPEED CURRENT TO VOLTAGE CONVERSION

Definition of Specifications

Integral Linearity Error, INL, is the measure of the worst

case point that deviates from a best fit straight line of data

values along the transfer curve.

ZO = 50Ω

CLK

RT = 50Ω

HI5780

DAC

FIGURE 9. AC TERMINATION OF THE HI5780 CLOCK LINE

Rise and Fall times and propagation delay of the line will be

affected by the Shunt Terminator. The terminator can be

connected to DGND.

Noise Reduction

To reduce power supply noise, separate analog and digital

power supplies should be used with 0.1µF and 0.01µF

ceramic capacitors placed as close to the body of the

HI5780 as possible on the analog (AVDD) and digital (DVDD)

supplies. The analog and digital ground returns should be

connected together back at the device to ensure proper

operation on power up.

Differential Linearity Error, DNL, is the measure of the

step size output deviation from code to code. Ideally the step

size should be 1 LSB. A DNL specification of 1 LSB or less

guarantees monotonicity.

Output Voltage Full Scale Settling Time, is the time

required from the 50% point on the clock input for a full scale

step to settle within an 1/2 LSB error band.

Glitch Area, GE, is the switching transient appearing on the

output during a code transition. It is measured as the area

under the curve and expressed as a Volt-Time specification.

Differential Gain, ∆AV, is the gain error from an ideal sine

wave with a normalized amplitude.

Differential Phase, ∆Φ, is the phase error from and ideal

sine wave.

Spurious Free Dynamic Range, SFDR, is the amplitude

difference from a fundamental to the largest harmonically or

non-harmonically related spur. A sine wave is loaded into the

D/A and the output filtered at 1/2 the clock frequency to elim-

inate noise from clocking alias terms.

10-1722

Share Link: