HSP48410 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

比赛名单

HSP48410

Histogrammer/Accumulating Buffer

Intersil 

Pin Description

NAME

PLCC PIN

CLK

1

PIN0-9

3-11, 83

LD

FCT0-2

15

16-18

TYPE

I

I

I

I

START

14

I

FC

12

I

DIN0-23

58-63,

I

65-82

DIO0-23

33-40,

I/O

42-57

IOADD0-9

22-31

I

UWS

21

I

WR

19

I

RD

13

I

VCC

GND

2, 32

20, 41, 64, 84

NOTES:

1. An overbar denotes an active low signal.

2. Bit 0 is the LSB on all busses.

HSP48410

DESCRIPTION

Clock Input. This input has no effect on the chips functionality when the chip is programmed

to an asynchronous mode. All signals denoted as synchronous have their timing specified

with reference to this signal.

Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on-chip RAM

with address values in Histogram, Bin Accumulate and LUT(write) mode. During Asynchro-

nous modes it is unused.

The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below).

These three pins are decoded to determine the mode of operation for the chip. The signals

are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the

loading of this function is asynchronous to CLK, it is necessary to disable the START pin dur-

ing loading and enable START at least 1 CLK cycle following the LD pulse.

This pin informs the on-chip circuitry which clock cycle will start and/or stop the current mode

of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously

started and stopped. This input is sampled by the rising edge of CLK. The actual function of

this input depends on the mode that is selected. START must always be held high (disabled)

when changing modes. This will provide a smooth transition from one mode to the next by

allowing the part to reconfigure itself before a new mode begins. When START is high,

LUT(read) mode is enabled except for Delay and Delay and Subtract modes.

Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits

in the RAM Array and the input and output data paths to zero.

Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and

Delay and Subtract modes. Synchronous to CLK.

Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the

memory array and reading the results of the previous operation. Configurable as either a 24

or 16-bit bus.

RAM address in asynchronous modes. Sampled on the falling edge of WR or RD.

Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of

DIO0-7 as being the upper eight bits of the data in or out of the Histogrammer. A zero means

that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect.

Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one

of the asynchronous modes. Asynchronous to CLK.

Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23

in other modes. Asynchronous to CLK.

+5V. 0.1µF capacitors between the VCC and GND pins are recommended.

Ground

4

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