HSP48410 查看數據表（PDF） - Intersil

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HSP48410

Histogrammer/Accumulating Buffer

Intersil 

Functional Block Diagram

HSP48410

DIO DIO 0-23

I/F

DIN 0-23

MUX

24X1024

RAM

IN

OUT

ADDRESS

IOADD 0-9

PIN 0-9

ADDRESS

GENERATOR

ADDER

INPUT

∑

CONTROL

MUX

CLK

WR

RD

UWS

START

FC

COUNTER

CONTROL

TO ADDRESS GENERATOR

TO OUTPUT STAGE

TO RAM

FCT 0-2

LD

FUNCTION

DECODE

MUX

CONTROL

SIGNALS

ALL REGISTERS ARE CLOCKED BY CLK

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

Histogram Mode

This is the fundamental operation for which this chip was

intended. When this mode is selected, the chip configures

itself as shown in the Block Diagram of Figure 2. The pixel

data is sampled on the rising edge of clock and used as the

read address to the RAM array. The data contained in that

address (or bin) is then incremented by 1 and written back

into the RAM at the same address.

RAM

IN OUT

WR

ADDRESS

S

“0”

PIN 0-9

ADDRESS

GENERATOR “1”

DIO

DIO 0-23

I/F

RD

START

CONTROL

FIGURE 2. HISTOGRAM MODE BLOCK DIAGRAM

At the same time, the new value is also displayed on the DIO

bus. This procedure continues until the circuit is interrupted

by START returning high. When START is high, the RAM

write is disabled, the read address is taken from the Pixel

Input bus, and the chip acts as if it is in LUT(read) mode.

Figure 3 shows histogram mode timing. START is used to

disregard the data on PIN0-9 at DATA2. START is sampled

on the rising edge of clock, but is delayed internally by 3

cycles to match the latency of the Address Generator. Data

is clocked onto the DIO bus on the rising edge of CLK. RD

acts as output enable.

CLK

START

PIN 0-9

DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5

DIO 0-23

(RD LOW)

OUT 0 OUT 1 OUT 2

ORIGINAL BIN CONTENTS

ARE NOT UPDATED

FIGURE 3. HISTOGRAM MODE TIMING

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