HSP3824 查看數據表（PDF） - Harris Semiconductor

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HSP3824

Direct Sequence Spread Spectrum Baseband Processor

Harris Semiconductor 

HSP3824

defeated by listening to one of the scrambling spectral lines

since the unintentional receiver in this case is too narrow band

to recover the data modulation. This assumes though that

each user can set up different scrambling patterns There are

9 maximal length codes that can be utilized with a generator

of length 7. The different codes can be used to implement a

basic privacy scheme. It needs to be clear though that this

scrambling code length and the actual properties of such

codes are not a major challenge for a sophisticated intentional

interceptor to be listening in. This is why we refer to this

scrambling advantage as a communications privacy feature

as opposed to a secure communications feature.

Scrambling is done by a polynomial division using a pre-

scribed polynomial. A shift register holds the last quotient

and the output is the exclusive-or of the data and the sum

of taps in the shift register. The taps and seed are program-

mable. The transmit scrambler seed is programmed by CR

15 and the taps are set with CR 16. Setting the seed is

optional, since the scrambler is self-synchronizing and it

will eventually synchronize with the incoming data after

flashing the 7 bits stored from the previous transmission.

Modulator Description

The modulator is designed to support both DBPSK and

DQPSK signals. The modulator is capable of automatically

switching its rate in the case where the preamble and header

are DBPSK modulated, and the data is DQPSK modulated.

The modulator can support date rates up to 4 MBPS. The pro-

gramming details of the modulator are given at the introduc-

tory paragraph of this section. The HSP3824 can support data

rates of up to 4 MBPS (DQPSK) with power supply voltages

between 3.3V and 5.0V and data rates of up to 3 MBPS with

supply voltages between 2.7V and 5.5V.

Clear Channel Assessment (CCA) and

Energy Detect (ED) Description

The clear channel assessment (CCA) circuit implements the

carrier sense portion of a carrier sense multiple access

(CSMA) networking scheme. The Clear Channel Assess-

ment (CCA) monitors the environment to determine when it

is feasible to transmit. The result of the CCA algorithm is

available in real time through output pin 32 of the device. The

CCA state machine in the HSP3824 can be programmed as

a function of RSSI, energy detected on the channel, carrier

detection, and a number of on board watchdog timers to

time-out under certain conditions. The CCA can be also

completely by-passed allowing transmissions independent of

any channel conditions. The programmable CCA in combi-

nation with the visibility of the various internal parameters

(i.e. Energy Detection measurement results), can assist an

external processor in executing algorithms that can adapt to

the environment. These algorithms can increase network

throughput by minimizing collisions and reducing transmis-

sions liable to errors.

There are two measures that are used in the CCA assess-

ment. The receive signal strength (RSSI) which measures

the energy at the antenna and the carrier sense (CS), which

is triggered upon valid PN correlation of the baseband pro-

cessor (HSP3824). Both indicators are used since interfer-

ence can trigger the signal strength indication, but it will not

trigger the carrier sense. The carrier sense, however, is

slower to respond than the signal strength and it becomes

active only when a spread signal with identical PN code has

been detected, so it is not adequate in itself. Note that the

CS is also vulnerable to false alarms. The CCA looks for

changes in these measurements and decides its state based

on these measures and the time that has elapsed since the

CONTINUOUS

CCA TO MAC

ED

WAIT FOR CHANGE

IN ED OR CS STATUS

CS

OR TIMER TIMEOUT

WATCHDOG TIMER

RESET ON CCA = CLEAR

RESET ON M ms TIMEOUT

RESET

ED >THRESH

ED >THRESH

CS < THRESH

ED < THRESH

CS< THRESH

ED < THRESH

CLEAR

CCA

LATCH

HOLDS

LAST

DECISION

CS > THRESH

ED < THRESH

BUSY

BUSY

BUSY

CS > THRESH

ED > THRESH

CNT = CNT + 1

RESET CNT

CNT < N

CLEAR

CNT = N

RESET CNT

FIGURE 13. CCA FUNCTIONAL FLOW DIAGRAM

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